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As the semiconductor industry slowly recovers from the economic downturn, it’s facing an accelerated technology roadmap and shortened product lifecycles. The semiconductor manufacturer’s challenge is to balance the time to introduce new technologies with reasonable investment costs at minimized risk. Lithography exposure tools are often the most expensive
in the wafer fab and therefore dominate miniaturization progress. Patterning of many layers in integrated circuit manufacturing requires a large number of exposure tools, resulting in high total costs for lithography equipment.
If the past trend in circuit size reductions is to continue there must be continued development in lithographic technology. But, lithography development faces severe challenges to deliver the capability to produce reduced size features and increased control year after year. At the same time it must do so at greatly reduced cost.
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