As the semiconductor industry slowly recovers from the economic downturn, it’s facing an accelerated technology roadmap and shortened product lifecycles. The semiconductor manufacturer’s challenge is to balance the time to introduce new technologies with reasonable investment costs at minimized risk. Lithography exposure tools are often the most expensive in the wafer fab and therefore dominate miniaturization progress. Patterning of many layers in integrated circuit manufacturing requires a large number of exposure tools, resulting in high total costs for lithography equipment.

Lloyd Litt
Motorola Inc., Semiconductor Products Sector

Once upon a time…the semiconductor industry was a very good business. Investments to build fabs and develop technology were large, but there were equally large potential returns as the consumption of chips grew at a rapid pace. There were historic ‘boom and bust’ cycles but these tended to be short and a large company could easily ride out the down years and continue to invest in development to support the future up swings. It has been quite some time since the semiconductor industry has experienced the profits and growth that had been enjoyed in the past and this downturn is headed for record duration. Even though most semiconductor manufacturers are experiencing low profits and are taking drastic ‘survival’ actions to stay afloat, the advancement of technology development continues. The rate of the advancement has been slowed, but it does continue. If the recovery continues to languish the ‘survival’ actions may include severe cutbacks in development funding which will further slow the pace of technology development.

If the past trend in circuit size reductions is to continue there must be continued development in lithographic technology. But, lithography development faces severe challenges to deliver the capability to produce reduced size features and increased control year after year. At the same time it must do so at greatly reduced cost.

The question now becomes “What is the most cost effective method that allows continued progress toward meeting the general roadmap goals?”. The development of EUV lithography has been, and will continue to be, a very costly endeavor. There have been some delays in the development schedule and it is likely that the delays will continue given the current economic situation. The development of 157 nm lithography has also had its share of problems. Several key technology issues remain to be solved for 157 nm to be used in manufacturing. The lack of a pellicle solution is one of the more obvious issues that must be resolved.

The surfacing of immersion lithography as a potential solution adds to the development options. However, it also divides the development efforts and dilutes the overall effectiveness of this work. Immersion lithography has some very attractive advantages but also requires a significant amount of work to solve some basic engineering problems in a relatively short timeframe. If the problems with immersion are not solved before the problems with 157 nm are worked out then immersion lithography may be scuttled and all the effort to develop the technology could be wasted. The converse is also true. As in most things, timing is extremely critical.

This issue of Future Fab includes several articles that address the issues associated with the future directions of lithography development. Prof. Bruce Smith, et. al., from R.I.T provides an overview of immersion lithography theory and the issues faced by the industry in implementing this technology. Dave Bergeron, et. al. addresses the use of OPC to extend current lithographic systems to the 90nm node and beyond. Obviously many of the OPC methods discussed could also be applied to immersion, 157 nm, and EUV equally well as the K1 factors shrink in the future. Finally, an article on the impact of EUV mask defects on cost and manufacturing logistics is explored by L. Litt et. al. The importance of particulate defects on reticles has become highlighted for EUV since there is no traditional protective pellicle material solution available for EUV use. However, the principles of inspection and cleaning frequency scenarios can be applied to any wavelength system to study and optimize manufacturing risk and cost implications.

Ernst Richter
Fab Cluster Site Representative, Infineon Technologies AG

As the semiconductor industry slowly recovers from the economic downturn, it’s facing an accelerated technology roadmap and shortened product lifecycles. The semiconductor manufacturer’s challenge is to balance the time to introduce new technologies with reasonable investment costs at minimized risk. Lithography exposure tools are often the most expensive in the wafer fab and therefore dominate miniaturization progress. Patterning of many layers in integrated circuit manufacturing requires a large number of exposure tools, resulting in high total costs for lithography equipment.

In order to follow the international technology roadmap for semiconductors (ITRS) requirements for smaller dimensions adjustment of the whole lithographic infrastructure, i.e. exposure tool, mask, photoresist, and process is required. Traditionally, reducing the exposure wavelength has been the trend for the exposure tools. Resolution enhancement techniques (RETs), like off axis illumination (OAI), phase shifting masks (PSMs), and optical proximity correction (OPC) have allowed extended usage of existing tools as cost effective solutions in manufacturing. Due to the ever-reduced development cycles for each wavelength generation, more drastic RET’s are required to extend the working lifetime of exposure systems and ensure sufficient technology maturity.

This issue of Future Fab International addresses RET’s for future optical lithography and gives an outlook on next generation lithography mask issues.

David Bergeron et al, describe tailored lithography strategies for the 90 nm node and beyond with focus on device and interconnect levels. The interdependencies of lithographic infrastructure are thoroughly investigated with respect to the appropriate RET’s. Exposure tool approaches include OAI for ArF and KrF; mask methods are calibrated model-based OPC, weak and strong PSM’s. A bi-layer resist system was also used for thin film imaging. In collaboration with Synopsis and Canon, Applied Materials proved the process capability in pilot integration. Advanced RET’s such as the Vortex PSM have also been explored, enabling near optical-limit resolution.

Bruce Smith et al, describe the opportunities and challenges of water immersion ArF lithography. By inserting a layer of liquid between projection lens and wafer permits notably finer resolution than traditional lithography. This involves only small changes in the optical train. Immersion lithography could be the easiest way to push both ArF and F2 lithography into two additional device generations, providing additional time for the solution of critical issues for upcoming imaging technologies. Working prototype systems exist and issues are carefully examined. Water is an attractive choice as immersion fluid for ArF mainly due to its optical properties. A fundamental issue is the compatibility of water with lithographic systems. These include imaging capability (e.g. polarization effects), fluid properties (e.g. micro-bubbles), and photoresist interactions. Critical research is economical and in cost estimations, several components like throughput must also be considered.

As already adverted in the previous edition an outlook on extreme ultra violet (EUV) lithography without pellicles is given by Lloyd Litt et al.. The inability to use a pellicle is due to the membrane absorption at EUV. Inspection and cleaning frequency requirements are examined on the basis of a cost of ownership (CoO) analysis. By this outlook it is possible to anticipate many of the implications for next generation lithography that can also be substantially transferred to current practices. Ernst Richter Fab Cluster Site Representative, Infineon Technologies AG