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Photostabilization Optimization of N-Well and P-Well Resist Processes
(7/1/2000) Future Fab Intl. Issue 8
By Dave Harris, LSI Logic Corporation
Donna Whiteside, Eaton Corporation - SEO, Fusion Systems Division
Robert Mohondro, Tevet Process Control Technologies
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Introduction

Photostabilization has repeatedly proven to reduce many of the problems associated with resist modifications during implant by cross-linking the photoresist to prevent profile changes and removing solvents and nitrogen that cause outgassing during implantation. In addition, because 100% of the resist is cross-linked, and a significant quantity of solvent is removed during the cure process, outgassing during implantation is reduced, providing a more controlled placement of ions. Ultimately, a properly designed photostabilization process has the potential to drastically improve resist pattern integrity throughout the implant process. By adjusting the sidewall angle through photostabilizer changes, robust inter-well isolation can be created and preserved[1, 2].

At LSIs Colorado 200 mm wafer fabrication facility, across the wafer device parametric analysis indicated a possible process capability issue associated the devices N and P-well implant regions. A resist pattern integrity issue was thus suspected. An evaluation of processing equipment that could potentially cause this effect was conducted. A direct correlation between resist profiles and device parametrics was discovered on wafers which were processed through the FusionGemini Photostabilizer. Atomic Force Microscopy indicated a consistent critical dimension gradient from top left to lower right. Similarly, resist cross sections indicated resist shrinkage in the top left and resist swelling in the lower right wafer quadrants. These gradients in both critical dimension and resist angle directly translated into the reduction in process capability seen parametrically.

Process Description

N-well and P-well images are created using Shipley SPR518 resist coated at a thickness of 2.7 m. Wafers were softbaked at 90C for 90 seconds, post exposure baked at 110C for 60 seconds, and then developed. No post develop bake was performed. (Photostabilization is most effective when hard bakes are omitted.) The wafers were then photostabilized on an Eaton FusionGemini Photostabilizer to prepare the resist for high-energy Boron and Phosphorus implants. After implantation, the resist was stripped using a plasma asher followed by a wet clean in piranha to remove residues.

Experimental

Twenty-five wafers were processed through the standard production processes. Wafer order was carefully documented through the coat, exposure, develop, photostabilization cure and implant steps. Photo processing was performed on the same stepper, and one chamber of the dual chamber FusionGemini PS System was used for photostabilization. N-well implant was used because of its high energy and was expected to cause the most damage or change in resist. Measurements were taken of wafers in slots 1, 2, 12, 13, 24, and 25. Critical Dimension (CD) measurements were tabulated and graphed, after develop, cure, and implant. Measurements indicted that the majority of CD loss was due to the photostabilization process of record (POR) as seen in Figure 2.

Figure 2. N-Well and P-Well Process of Record (POR) CD variation

Tests were then conducted on the Photostabilization process to determine the root cause of the loss in CD control, resist shrinkage and resist swelling. Photostabilization factors were; idle temperature, ramp rate, lamp powers and bulb type (H-Mod vs D-Mod). These process factors and responses were analyzed to determine a process with minimum impact on photoresist image integrity and provide maximum allowable throughput. Figure 3 shows the results from non-optimization of the aforementioned parameters.

Figure 3. Cross sectional inspections of POR sidewall profiles.

The characterization process was started with the initial photostabilization process changes shown in Table 1. Optical inspection of the POR revealed intermittent blistering throughout the wafer. The blistering was completely eliminated by reducing the photostabilization idle temperature and extending the pre-exposure time (lamp exposure at the idle temperature) by 20 seconds. The lamp power (required to cross-link resist) was increased from 150mW/cm2 to 275mW/cm2 (normal high lamp setting). Table 1 illustrates the photostabilization program changes. The DOE determined that the D-Mod bulb, with its longer wavelength, made a significant impact on the results (Figure 4). Subsequent testing verified that the bulb change was indeed a significant contributor to the process improvement (Figure 5). The SEM photos (Figure6) of identical areas on various wafers clearly demonstrates the importance of bulb selection, idle temperature and bulb power.

Figure 4. Spectral comparison of H-Mod and D-Mod bulbs.

Figure 5. Cross sectional inspections of resist sidewall profiles of identical areas, (the only process change was the bulb type.)

Table 1. Photostabilization Process of Record parameters and a preliminary experimental process for the thick film (2.7m) process.

POR Preliminary Sidewall investigation

Additional investigation of lamp powers effects on sidewall changes was conducted. Table 2 shows the comparison of the POR against the new optimized process. Figure 7 shows the SEM cross section of the resist structures after develop, POR (failed structures) and after optimization. Any changes to resist profile would have never been observed without cross-sectional SEM Inspection since top-down SEM does not allow for views of sidewall profiles if a negative angle is present.

Table 2. Photostabilization Process of Record parameters and the Optimized process parameters for the thick film (2.7 m) process.

After optimizing the process with the D-Mod bulb a complication arose. Eatons updated recommendation for thick resist (>2.0uM) is to use the D-Mod bulb as it yields superior process results. This is due mainly to the slow photoresist cross-linking effects by the longer wavelengths of the D-Mod bulb. However, the process of record used the H-Mod bulb, which was also used for thinner resist applications. The H-Mod bulb works very well for most photoresist thicknesses below 2.0m. To avoid tool dedication due to the bulb change for the 2.7 m processing, thin photoresist processes were also created using the D-mod bulb. Results of the thinner resist showed no negative impact on patterning integrity and resulted in the added benefit of a reduced cycle time of 15 seconds per wafer. The optimized process for thin photoresists using the D-Mod bulb is shown in Table 3.

Figure 6. Cross sectional inspections of resist sidewalls comparing the post develop structure, the photostabilization POR and the preliminary experimental process results.

Figure 7. Cross sectional inspections of sidewall comparing the Post develop structure, the POR and the optimized process

Table 3. Photostabilization process of record parameters and the optimized process parameters for thin photoresist (1.57 m) process.

Results

An additional benefit observed through this optimization, was the reduction of photoresist outgassing during ion implantation. One of the most common problems at ion implant is the outgassing of the resist. If implanter pressure changes due to outgassing is encountered, dose control is difficult to maintain. The quantity and significance of this outgassing is determined by the implant parameters such as energy, species dose and current applied. As can be seen in Figure 8, outgassing during implant was significantly reduced once the process was optimized at the photostabilization step. This reduction in outgassing can lead to improved implanter throughput.

Figure 8. Ion implanter outgassing reduction through process optimization of the photostabilization process.

Another benefit of the optimization was the improvement in throughput. The optimized process for the thick photoresist process yielded a 50-second reduction in process time while a 15-second process time reduction was provided for the thin photoresist processes. Both of these cycle time reductions translate into additional cost savings when a Cost of Ownership calculation is done for the entire process cluster.

Conclusion

This project has stressed the importance of process optimization. What originally appeared to be a minor uniformity adjustment to a non-critical level improved both the pattern integrity and the overall Cost of Ownership. Variations in critical dimension and sidewall profile need greater attention today and in the future as feature sizes (eg transistor formation in ICs) continue to decrease.

Additionally, improvement in wafer throughput for both thick and thin photoresist processes was realized.

References

[1] P. Gilbert, J. Grant, P. Tsui, C. King, W. Taylor, K. Wimmer, The Impact of Photoresist Taper and Impact Tilt Angle on the Interwell Isolation of Sub-Quart Micron CMOS Technologies.

[2] R. Mohondro, J. Eisele, D. Whiteside, T. Romig, M. Bishop, Photostabilzation: The Process of Improvement, Future Fab International, Vol.3.

Biography

Dave Harris is a Photolithography Process Engineer at LSI Logic Colorado. He has worked in the semiconductor industry for 5 years and is currently focusing on improved resist cures.

 

Warren Greene is the Photolithography Process Group Leader at LSI Logic Colorado. He has 10 years experience in semiconductor lithography.

 

Crystal Hass is currently working as an Implant Process Engineer at LSI Logic Colorado. Crystal has 10 years experience in the semiconductor field in both implant and device engineering.

Donna Whiteside is a Process Engineer with the Eaton Corporation, Fusion Systems Division, specializing in Photostabilization of thick photoresists and I-line resist. Donna has co-authored several technical papers on Photostabilization dealing with etch and implantation. She has worked in the semiconductor industry for over 10 years and before joining, Eaton worked for IBM.

 

Robert Mohondro is the Process Program Manager, Eaton Corporation, Fusion Systems Division. Prior to joining Eaton, Mr Mohondro was Vice President of Engineering for the Advanced Lithography Group where he was working on ion projection lithography. He has over 25 years of experience in the semiconductor industry and has held management or supervisory positions at the ALG, MTI, National Semiconductor, MMI, and Intel. He has authored numerous papers on resist processing, lithography (optical and ion projection), polyamide processing, particle control and photostabilization. He is a member of SPIE.

 
 
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