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FUTURE FAB ARCHIVES


Cycle Time Reduction: Systematic Six-sigma Approach
(2/11/2003) Future Fab Intl. Issue 14
By Anurag Lodha, Seagate
Linda Hanson, Seagate
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The impact of wafer starts methodology on wafer build cycle time is presented. The Six-Sigma process improvement approach was utilized to identify Key Process Input Variables (KPIVs) affecting wafer build cycle time, and implement methods to reduce overall cycle time with negligible impact on factory personnel or work flow. Process improvements were achieved with no additional cost. Cycle time was reduced by 10% for the initial processing stage (Stage I) in wafer build when daily wafer starts frequency was increased from two times per day to six times per day.

Cycle time improvements may be achieved by optimizing the throughput of individual manufacturing processes. The scope for improvements in cycle time related to individual processes is generally limited, however, by material and equipment factors such as tool capability, consumable material reliability, and other operational parameters[1]. Improvements at this micro-level are critical for bottleneck areas where cycle time is adversely impacted by resource constraints. Conversely, cycle time improvements at the macro-level address systemic issues involving production scheduling, planning, and capacity[2].

Introduction

Cycle time improvements may be achieved by optimizing the throughput of individual manufacturing processes. The scope for improvements in cycle time related to individual processes is generally limited, however, by material and equipment factors such as tool capability, consumable material reliability, and other operational parameters[1]. Improvements at this micro-level are critical for bottleneck areas where cycle time is adversely impacted by resource constraints. Conversely, cycle time improvements at the macro-level address systemic issues involving production scheduling, planning, and capacity[2].

Understanding the salient features of the synergistic relationship between micro- and macro- level factors may be key to achieving significant time-reductions. However, considerable effort is required in order to realize significant sustainable improvements. For this reason, the goal should be the application of a robust method that is cognizant of the requirements of each approach.

This paper details a cycle-time reduction project undertaken in our wafer fabrication facility. The Six-Sigma methodology was utilized as a systematic, data-driven process improvement approach. This cross-functional, disciplined technique facilitated identification of the KPIVs that effect wafer build cycle time, and implementation of a no-cost solution to reduce overall cycle time which was virtually transparent to the shop floor.

Background

The practice in our 24/7 factory is to issue wafer starts twice daily i.e. at the beginning of each 12-hour production shift, illustrated in Figure 1. During the course of a (Phase I) Six-Sigma content-reduction/optimization project, the process cycle time was quantified as an ancillary improvement metric. The significant cycle time variability observed, and the intuitive appeal of the notion that the wafer starts protocol exerts significant influence on overall wafer build cycle time, formed the basis of the work presented here.

Figure 1. Historical wafer starts.

In practice, the regimen adopted by factory production control, ostensibly formulated with input from both industrial engineering and the shop floor, should yield optimal WIP flow. This consensus should result in logical batch sizes that ensure an even flow of wafers at the tools and with zero queue time (see Figure 2).

Figure 2. Queue time reduces if lots are staggered in batch size that matches tool capacity at the next process.

The average queue time at any given process step can be calculated from the following equation[3]:


Where
CTq average queue time at station,
ca coefficient of variation of time between arrivals to a station,
ce coefficient of variation of effective process time at a station,
u equipment utilization, the fraction of time equipment is not idle for lack of parts,
te mean effective process time including setup time, downtime etc.

The coefficient of variation is related to the mean and standard deviation by the following equation:

Where
s = standard deviation of time
t = average time

Methodology

The framework utilized and key components of each follow (illustrated in Figure 3):
• Define: Problem statement; improvement metrics and goals; team members
• Measure: Quantification of the problem; cause and effect; Key Process Output Variables (KPOVs)/KPIVs
• Analyze: Statistical analysis (hypothesis testing, capability, time-series, etc.)
• Improve: Design of Experiments (DOE) utilizing controllable KPIVs.
• Control: Implementation of process control Statistical Process Control (SPC), Shop Floor Control (SFC), Statistical Throughput Control (STC), etc. on KPIVs identified in Improve phase to ensure sustained improvements.

Figure 3. Identifying key process input variables determined from cause-effect diagram.

Primary Metric

The first step was to determine the metric to measure improvements in cycle time. Initially the complete wafer build cycle time was thought to be an appropriate metric. Due the very high level of complexity in the fab, with factors like varying product mix, changing WIP levels, tool uptime, hot lots, yield, other ongoing process changes and improvements etc., it was concluded that the actual cycle time change from the proposed project would be hidden or lost in the complexity of the fab. As illustrated in Figure 4, the initial stage in the wafer build involving about nine different process steps was found to be the same for all products. Assuming that cycle time for these steps in not influenced by factors listed above, the primary metric was chosen to be the cycle time for this stage.

Figure 4. Complexity in process flow maps and products in a fab. Numbers 1 to 9 indicate process steps that form a stage.

Measure

The objective in the measure phase was to determine all the factors that effect wafer build cycle time. This also allowed for all concerned people to get on one platform and also accept the changes that would follow.

Cause and Effect Diagram

A cross-functional team involving operators, trainers, engineers, managers, and senior management was formed to develop a cause and effect diagram to identify the KPIVs that effect cycle time. Figure 5 shows several human and non-human factors that were listed by the team.

Figure 5. Cause and effect diagram for built wafer cycle time.

Analyze

The objective of this phase was to identify the KPIV that would be a part of this project, to implement proposed solutions, and analyze the effect of the changes implemented.

What is the KPIV?

The effect of staggering the wafer starts was chosen to be the KPIV, since it aligned with the objective to reduce cycle time without any significant change in the way factory operates, no change in tooling, and foremost being at no additional cost. The cause-effect diagram developed also formed a basis for management to initiate other cycle time reduction projects. The wafer starts were staggered in six equal intervals as shown in Figure 6 for three weeks. This was achieved by releasing one-sixth of the daily wafer starts four-hour intervals.

Figure 6. Wafer starts evenly staggered in six equal intervals for each day.

Figure 7. Two sample t-Test to compare non-staggered vs. staggered wafer starts.

Test of Hypothesis

One-sample t-Test was done to determine if there was a significant change in the cycle time when wafer starts were staggered more frequently. Sample size required for the statistical test was determined with the objective to see critical difference of 10% or more, with 95% confidence interval (a = 0.05), and power of test to be greater than 90% (b = 0.1). The cycle time standard deviation was based on the historical data.



Based on the above set values, the number of samples required from each sample set was determined to be cycle time of 197 wafers. The sample data for statistical analysis was more than the minimum required since data was collected over a period of two weeks, to include variations such as changing shifts for each week.

Figure 7 shows the results for the test of the above hypothesis. Based on the p-value, it can be concluded that the cycle time for the staggered starts is significantly less than the cycle time for non-staggered starts. The power of this statistical test based on actual sample size was 96% (E = 0.04). This implies that there is 96% probability that a difference will be detected when there actually is a difference.

Improve and Control

The above results quantify the effect of wafer starts methodology on cycle time. Based on these results, our management decided to implement staggered wafer starts methodology as done in this study.

Conclusion

This study shows that staggering wafer starts into small batches has a significant impact on cycle time. By increasing the frequency of starts from two times a day to six times a day, 10% reduction in cycle time for the first stage in wafer build was achieved. There is perhaps an optimum batch size and time interval beyond which there may not be significant improvement in cycle time. In extreme cases, reducing the time interval to too small units may lead to tool starvation and reduce equipment utilization.

Acknowledgement

The authors would like to acknowledge the assistance provided by James Bissonnette, Donald Haupert, Collen Tushaus, Donald Haupert, Scott Conklin, Daniel Rgnonti, Jon Albachten, Wanda Mooney, Jeff Stanczak, Con Hemmesch, and Jerry Hedtke in developing the cause-effect matrix. The authors also thank Kevin Harnisch and Jeffrey Melnick for their support throughout the project.

References

[1] Peter Gaboury, “Equipment Process Time Variability: Cycle Time Impacts”, Future Fab International, Issue 11, p.163. Or see it online at http://www.future-fab.com/documents.asp?d_ID=637.

[2] Yoshinobu Hayashi, Yasushi Kodashima, and Mitsuyuki Yamaguchi, “Semiconductor Equipment Design for Short Cycle Time Manufacturing”, Future Fab International, Issue 10. See it online at http://www.future-fab.com/documents.asp?d_ID=1154

[3] Wallace J. Hopp and Mark L. Spearman, “Factory Physics: Foundations of Manufacturing Management”, 2000, Mc-Graw Hill, Chapter 8.

Biographies

Anurag Lodha

Anurag Lodha received the B.S. degree with honors in Chemical Engineering from University of Rajasthan, Jaipur, India, in 1996, and the M.S. degree in Chemical Engineering from the Clemson University, SC, USA, in 2000. From August 1996 he worked, as was Junior Research Fellow at Center for Environmental Science and Engineering, Indian Institute of Technology, Bombay, India. Before continuing with graduate studies, he worked briefly from January 1998 to June 1998 at Essar Investments Limited (Environment, Risk, and Insurance Management Division, Group Corporate), Bombay, India. After completing his graduate studies, he joined Seagate Technology, LLC. at their Recording Head Operations in Minnesota, where he is primarily working in the area of CMP and wafer cleaning.

Linda Hanson

Linda Hanson received the B.A. degree in Chemistry in 1994, graduating with honors from the College of Saint Catherine, St. Paul, Minnesota. Upon graduation, she completed the M.S. degree in Chemistry at Purdue University, West Lafayette, Indiana in 1997. After completing graduate studies, she returned to Minnesota to join Seagate Technology, LLC. After holding several positions at Seagate including wafer process engineer and Six Sigma Black Belt, she is currently functioning as a Supplier Quality Engineer.

Contacts

Anurag Lodha
Advisory Manufacturing Engineer
Seagate Technology LLC
NRE 220
One Disc Drive
Bloomington, MN 55435
Phone: +1-952-402-8399
Fax: +1-952-402-7016
E-mail: Anurag.Lodha@seagate.com
Web: www.seagate.com

 
 
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