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The impact of wafer starts methodology on wafer build cycle time is presented. The Six-Sigma process improvement approach was utilized to identify Key Process Input Variables (KPIVs) affecting wafer build cycle time, and implement methods to reduce overall cycle time with negligible impact on factory personnel or work flow. Process improvements were achieved with no additional cost. Cycle time was reduced by 10% for the initial processing stage (Stage I) in wafer build when daily wafer starts frequency was increased from two times per day to six times per day. Cycle time improvements may be achieved by optimizing the throughput of individual
manufacturing processes. The scope for improvements in cycle time related to individual
processes is generally limited, however, by material and equipment factors such
as tool capability, consumable material reliability, and other operational parameters[1].
Improvements at this micro-level are critical for bottleneck areas where cycle
time is adversely impacted by resource constraints. Conversely, cycle time improvements
at the macro-level address systemic issues involving production scheduling, planning,
and capacity[2].
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