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Atomic Layer Deposition for Advanced DRAM Applications
(2/11/2003) Future Fab Intl. Issue 14
By M. Gutsche, Infineon Technologies AG
Harald Seidl, Infineon Technologies AG
Thomas Hecht, Infineon Technologies AG
Stephan Kudelka, Infineon Technologies AG
Uwe Schroeder, Infineon Technologies AG
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DRAM technology has been a major driver of innovations in process technology and manufacturing equipment in the microelectronics industry. As the semiconductor industry migrates to ever smaller device geometries, new deposition process technologies will be required to meet the challenges posed by the demand for novel materials, the need to work with ever thinner films, and the necessity to deposit conformal films into structures with increasingly high aspect ratios (AR). Atomic Layer Deposition (ALD) is a very attractive new technology which will open up great opportunities for next generation integrated circuit fabrication. ALD has already demonstrated that it can overcome many of the limitations of current film deposition techniques. ALD has shown unparalleled step coverage performance, superb uniformity and film thickness control, as well as high film quality of dielectric and metal layers. This article reviews the use of ALD for advanced DRAM technology. Infineon is developing ALD films for sub-100nm DRAM capacitor applications and has fabricated industry-first fully functional DRAM chips using ALD Al2O3 as node dielectric in high aspect ratio trench capacitors. The superior performance of ALD technology will enable the scaling of trench DRAM cells well beyond 100nm feature size. It is believed that DRAM applications will once again be a major driving force as ALD is being introduced into mainstream semiconductor processing.

Over the last decades the semiconductor industry has witnessed an unprecedented trend in miniaturization of silicon-based devices and integrated circuits. Semiconductor technology is now entering the sub-100nm regime. As feature sizes approach ever smaller dimensions, process control at the atomic level will become increasingly important. This is true for both removal and deposition of material. Attempts to etch material with atomic level control, so-called Atomic Layer Etching (ALET), have been reported[1]. This technology, however, is still in its infancy and may not be utilized for some time to come. On the other hand, Atomic Layer Deposition (ALD) as a technique which allows film deposition with monolayer precision has matured substantially and is now being introduced into semiconductor processing[2]. Key ALD applications include the deposition of high-k dielectrics, metal electrodes, barriers, and spacers. Other novel and innovative ALD applications are on the drawing-boards. This article will focus on the use of ALD in advanced DRAM technology.

DRAM technology has been a major driver of innovations in process technology and manufacturing equipment in the microelectronics industry. As the semiconductor industry migrates to ever smaller device geometries, new deposition process technologies will be required to meet the challenges posed by the demand for novel materials, the need to work with ever thinner films, and the necessity to deposit conformal films into structures with increasingly high aspect ratios (AR). Atomic Layer Deposition (ALD) is a very attractive new technology which will open up great opportunities for next generation integrated circuit fabrication. ALD has already demonstrated that it can overcome many of the limitations of current film deposition techniques. ALD has shown unparalleled step coverage performance, superb uniformity and film thickness control, as well as high film quality of dielectric and metal layers. This article reviews the use of ALD for advanced DRAM technology. Infineon is developing ALD films for sub-100nm DRAM capacitor applications and has fabricated industry-first fully functional DRAM chips using ALD Al2O3 as node dielectric in high aspect ratio trench capacitors. The superior performance of ALD technology will enable the scaling of trench DRAM cells well beyond 100nm feature size. It is believed that DRAM applications will once again be a major driving force as ALD is being introduced into mainstream semiconductor processing.

Introduction

Over the last decades the semiconductor industry has witnessed an unprecedented trend in miniaturization of silicon-based devices and integrated circuits. Semiconductor technology is now entering the sub-100nm regime. As feature sizes approach ever smaller dimensions, process control at the atomic level will become increasingly important. This is true for both removal and deposition of material. Attempts to etch material with atomic level control, so-called Atomic Layer Etching (ALET), have been reported[1]. This technology, however, is still in its infancy and may not be utilized for some time to come. On the other hand, Atomic Layer Deposition (ALD) as a technique which allows film deposition with monolayer precision has matured substantially and is now being introduced into semiconductor processing[2]. Key ALD applications include the deposition of high-k dielectrics, metal electrodes, barriers, and spacers. Other novel and innovative ALD applications are on the drawing-boards. This article will focus on the use of ALD in advanced DRAM technology.

The Basics of Atomic Layer Deposition

As opposed to conventional CVD which is characterized by continuous deposition and concurrent flow of precursors, Atomic Layer Deposition is based on the sequential deposition of individual monolayers or fractions of a monolayer in a well controlled manner[3]. In ALD, the growth surface is alternately exposed to only one of two complementary chemical environments, i.e. individual precursors are supplied to the reactor one at a time. Exposure steps are separated by inert gas purge or pump-down steps in order to remove any residual chemically active source gas or by-products before another precursor is introduced into the reactor. Thus, ALD consists of a repetition of individual growth cycles. Each cycle is made up of a typical sequence: Flow of precursor 1 ‘ Purge ‘ Flow of Precursor 2 ‘ Purge (Figure 1). During each exposure step, precursor molecules react with the surface until all available surface sites are saturated. Precursor chemistries and process conditions are chosen such that no further reaction takes place once the surface is completely saturated. Surface saturation guarantees the self-limiting nature of ALD. Precursors are preferably overdosed so that process results become independent of potential slight variations in the amount of precursor supplied to the surface. Thus, surface chemistry governs film growth rather than a precise control of tool specific process parameters such as precursor flow and partial pressure. A known and constant thickness is deposited per growth cycle. Typically, deposition rates on the order of 0.1 – 1.0 Å/cycle are obtained with cycle times ranging from 1 to 10 seconds . Cycle time critically depends on saturation behavior, chamber volume, and reactor design. The film is grown in a layer-by-layer mode, and the total film thickness is given by the number of cycles. Due to the self-limiting nature of the surface reactions, ideally, overdosing of precursors does not bring about increased deposition. Therefore, exceptional across-wafer thickness uniformity and excellent step coverage on high aspect ratio features can be achieved with ALD.

Figure 1. Al2O3 ALD growth cycle: (a) Starting surface with OH groups and inert gas flow. (b) TMA pulse saturates the surface. An Al containing monolayer (or fraction of a monolayer) is deposited with methyl ligands at the surface. CH4 is liberated in the reaction. (c) Residual TMA and by-products are purged out of the reactor by flowing an inert gas. (d) The surface is now exposed to a water pulse. The H2O reacts with the methyl ligands to form OH groups on the surface. CH4 is generated as by-product. (e) A second purge step removes residual H2O and by-products.

Excellent conformality and fill capability come at the expense of slow deposition rates. However, many films of interest, such as dielectric layers in transistors and capacitors as well as barrier films are only a few nm thick so that throughput remains acceptable. In addition, as film thicknesses tend to become smaller with decreasing feature sizes, the deposition rate will be less of a concern for future technology nodes.

A simple and well established example of an ALD process is the deposition of alumina (Al2O3) using trimethyl aluminum (TMA = Al(CH3)3) and water. TMA and H2O are alternately supplied to the ALD reactor, separated by purge (or evacuation) steps in between (Figure 1). At 450K, an Al2O3 growth rate of 1.1 Å/cycle is obtained, which corresponds to the deposition of a fraction of a monolayer per cycle. The following half reactions take place[4]:

Al-OH(s) + Al(CH3)3 ‘ Al-O-Al(CH3)2(s) + CH4

Al-CH3(s) + H2O ‘ Al-OH(s) + CH4

where (s) indicates a surface species.

ALD growth rates typically show only a weak dependence on substrate temperature. The ALD process window with respect to temperature is fairly large. Beyond a certain upper temperature limit, however, thermally activated decomposition of precursors sets in. At very low substrate temperatures, incomplete growth reactions may result in an increased impurity level in the deposited film.

Novel and complex materials can be fabricated by combining two or more ALD processes. If chemistries and substrate temperature are chosen properly, two or more materials can be deposited sequentially or alternately by switching precursors. Thus, complex materials systems such as nanolaminates or compounds can be deposited with great compositional control[5], which may be difficult to achieve using conventional deposition techniques. Figure 2 shows a nanolaminate fabricated by alternately depositing thin layers of Al2O3 and Hf aluminate into high aspect ratio trenches using ALD.

Figure 2. Laminate structure made up of Al2O3 and Hf aluminate layers alternately deposited into high aspect ratio trenches by ALD. The images demonstrate excellent step coverage performance and very good control over layer thickness. The TEM image (a) was taken in the lower right corner of the trenches shown in (b) (Source: Genus)

ALD is considered to be a promising thin film deposition technology and has found widespread acceptance in the field of high-k dielectrics for both DRAM storage capacitor and CMOS gate applications. HfO2 and ZrO2 based materials are extensively being studied as potential replacement for existing SiO2 and SiON gate dielectrics[6]. HfO2, Al2O3, and Ta2O5 are well suited for DRAM capacitors[7,8]. Due to the high aspect ratios encountered in storage capacitors, ALD is a particularly attractive deposition technique. ALD also addresses the need for metal electrode deposition in DRAM capacitor and transistor gate applications.

In the interconnect area, ALD is extremely useful for scaling of barrier and seed layers. DRAM tungsten contacts are expected to reach aspect ratios of Ž 12:1 in the sub-100nm regime. Aspect ratios are less demanding for CMOS applications, but seamless fills are required to prevent copper from diffusing through dimple holes after CMP. ALD TiN barrier films can be employed to cope with increasing aspect ratios. Moreover, ALD W nucleation layers have been reported which result in greatly improved film conformality and serve as an excellent starting surface for the subsequent W bulk fill. In addition, TaN ALD and W based ALD films are under consideration as barrier layers in Cu metallization. ALD is well suited for these applications, as it allows the deposition of very thin and defect-free layers.

Spacer applications are another area where ALD may be advantageous. Al2O3 based diffusion barriers for FeRAM have also been reported. Etch stop layers consisting of highly etch resistant materials can likewise be deposited by ALD.

ALD Step Coverage Performance

Aspect ratios in DRAM capacitors will continue to increase as the industry moves into the sub-100nm regime. Values of AR=60:1 and higher are expected for trench DRAM capacitor structures in future technology generations. Excellent step coverage performance of deposition processes at small ground rules will thus be an essential asset. A fundamental understanding of the dependence of ALD step coverage on process conditions is required to assess the extendibility of ALD to smaller ground rules and higher aspect ratios[9].

In order to saturate the entire surface of a high aspect ratio structure with one of the ALD reactants, a sufficient amount of precursor has to be delivered to the wafer surface within a given time. Thus, the degree of conformality critically depends on precursor pulse time and precursor concentration or partial pressure. The exposure, which is the product of precursor partial pressure and time, is a useful measure of the number of precursor molecules available for adsorption. The amount of precursor that a specific location on the side wall of a feature on the wafer is exposed to depends on gas transport in the reactor and gas transport inside the feature. Species transport inside high aspect ratio features with lateral dimension on the order of 100 nm at pressures < 100 Torr is in the Knudsen regime where the mean free path of the gas molecules is larger than the feature size. It turns out that the time required for species transport inside high aspect ratio structures actually makes up a significant portion of the overall saturation or pulse time. When precursor molecules enter a trench-like structure from the top, they diffuse into it and start saturating the side walls in a self-limiting zipper-like manner from top to bottom. By choosing appropriate exposure conditions, perfect step coverage can be obtained. Figure 3 demonstrates close to 100 % step coverage of an 18 nm thick Al2O3 film in trenches with a minimal width of 80 nm at an aspect ratio of ~ 60:1. This result and additional simulations[9] show that ALD is exceptionally well suited for deposition into high aspect ratio features at ground rules well below 100 nm.

Figure 3. ALD features superb step coverage performance. The SEM images show close to 100% conformality for an 18nm thick Al2O3 film which was deposited by ALD into high aspect ratio trenches with a minimum lateral dimension of 80 nm and a final aspect ratio of ~ 60.

DRAM requirements

DRAM technology with its 1-transistor/1-capacitor concept has long been at the leading edge of integrated circuit miniaturization. DRAM capacitor scaling has played a central role in this effort. In order to assure sufficient data retention time, a charge storage capacitance of 25 - 35 fF/cell and cell leakage currents < 1 fA/cell are required and have to be maintained over the coming technology generations. Small cell size is crucial to allow minimal chip size and thus reduce chip cost. Three-dimensional capacitor structures with high aspect ratios are therefore commonly used in the DRAM industry. Infineon, Nanya, Winbond, and ProMOS as well as IBM and Toshiba for embedded DRAM utilize deep trench capacitors etched into the silicon substrate before the transistors are fabricated. Trench capacitors can endure a high thermal budget with temperatures in excess of 1000ºC. Stacked capacitors are used by companies such as Samsung, Micron, Elpida, and Hynix. They are built above the transistor level either over or under bitline. Crown and cup shaped capacitors are widespread. The thermal budget linked to stacked capacitor fabrication is much lower than that for trench capacitors.

With decreasing minimum feature size F there is less silicon real estate available for the capacitor. At constant capacitor aspect ratio, cell capacitance scales with 1/F2. The aspect ratio is primarily limited by etch constraints, geometrical limitations, and mechanical stability issues. Nonetheless, every effort will be made to maximize the capacitor surface area at a given ground rule. In trench DRAM technology, the capacitor surface area can be further increased by enlarging the trench circumference using silicon wet etch techniques. Surface roughening by growing hemispherical grain silicon (HSG) is another well established method to achieve area and thus capacitance increase[7].

High-k Dielectrics for DRAM Capacitors

Once the geometrical options to maintain sufficient capacitance at smaller ground rules have been exhausted, capacitor dielectrics with higher dielectric constant k offer an attractive path to achieving enhanced capacitance per area. Ta2O5 is the most widely studied high-k material with applications in the DRAM industry. The material is used in MIS capacitors in conjunction with a suitable top electrode such as TiN. Both CVD and ALD processes are known for the deposition of Ta2O5. Ta2O5 is suitable for stacked capacitor applications but does not withstand the thermal budget required for trench DRAMs. The class of materials which are suitable for trench DRAMs includes pure Al2O3, HfO2- Al2O3 compounds or laminates, and Hf silicates. These dielectrics are stable up to high temperature in contact with silicon and are being studied for CMOS applications as well. HfO2-Al2O3 also has attracted the attention of the stacked capacitor community [8]. Suitable ALD processes are available for both Al2O3 and HfO2. For implementation into trench capacitors, it is most straightforward to use a standard silicon-insulator-silicon (SIS) structure and replace the conventional nitride-oxide by a suitable high-k material. In a second step, the inner or top electrode may be replaced by a metal (MIS structure) in an effort to eliminate the poly silicon depletion layer. A long-term option would be to implement a metal-insulator-metal (MIM) structure in order to get rid of any interfacial layers with low dielectric constant at the silicon-dielectric interface in SIS or MIS capacitors. MIM structures such as Ru/Ta2O5/Ru have been reported for stacked capacitors. For trench DRAMs, there is no immediate need to look into the MIM option.

Integration of Al2O3 into Fully Functional Trench DRAM Chips

Infineon has successfully integrated Al2O3 SIS trench capacitors into 128 Mb DRAM chips exhibiting full functionality. A 170nm technology was used. ALD is an indispensable tool to achieve conformal coverage of the high aspect ratio trench structures with high quality Al2O3. The following process flow was used in the capacitor fabrication (Figure 4): After formation of the trench, Al2O3 was deposited by ALD. A post-deposition anneal was performed to densify the Al2O3 film. Then, poly silicon was filled into the trench. Following a poly recess, the Al2O3 film was removed in the upper portion of the trench and an isolation collar was formed. Finally, poly silicon was once again filled into the trench.

Figure 4. Process flow used to integrate a high-k dielectric into a trench DRAM capacitor. (a) After trench formation the high-k dielectric is deposited conformally into the trenches and a poly silicon fill is done. (b) The poly silicon inside the trenches is recessed and the exposed high-k layer is removed. (c) An isolation collar is put in place and the upper trench region is again filled with poly silicon.

A cross-sectional view of a fully integrated trench DRAM cell with Al2O3 SIS capacitor is shown in the TEM image of Figure 5. The insert (a) confirms the stability of the ~ 5nm thick Al2O3 layer. Al2O3 is extremely inert in contact with silicon. The image also demonstrates the polycrystalline nature of the Al2O3 after it has been subjected to the full thermal budget of the trench DRAM process. Insert (b) shows the intersection of the Al2O3 film and the SiO2 isolation collar. The image demonstrates that the Al2O3 was successfully removed prior to collar formation. A cell capacitance enhancement of 20% was achieved while leakage currents remained below 1 fA/cell. Interestingly, the fact that the Al2O3 is in a polycrystalline phase does not lead to any drastic increase in leakage current and demonstrates that amorphicity is not a prerequisite for excellent electrical properties. The retention characteristics of Al2O3 based DRAM cells was significantly improved over that of NO based cells (Figure 6). Reliability measurements on trench capacitors at package level revealed an extrapolated lifetime of more than 10 years (Figure 7). The wafer map in Figure 8 represents the test yield for 128 Mb chips with Poly-Si/ Al2O3/Si capacitors fabricated in 170 nm technology and demonstrates excellent wafer level yield. Excellent package level yields have also been achieved.

Figure 5. DRAM cell consisting of trench capacitor and array transistor. Al2O3 was deposited as node dielectric. Insert (a) shows the Al2O3 dielectric layer (~ 5nm). (b) gives a detailed view of the intersection of SiO2 collar and Al2O3 capacitor dielectric.

Figure 6. Retention curves for Al2O3 (blue) and conventional NO (green) node dielectric in a trench DRAM capacitor. Al2O3 features improved retention performance.

Figure 7. Reliability measurements at package level demonstrate more than 10 years lifetime for Al2O3 at operating conditions.

Figure. 8. Wafer map demonstrating excellent test yield achieved for 128 Mb chips with Poly-Si/Al2O3/Si capacitors fabricated in 170 nm technology.

Electrical results depend to a large degree on the pre-treatment of the silicon surface before ALD deposition and on the post-treatment applied after Al2O3 deposition. Poly-Si deposition conditions also play an important role. Various interface preparation techniques were compared including wet and RTP treatments. It is known that a suitable starting surface is required in order to achieve uninhibited layer-by-layer growth at the start of the ALD deposition. A thin oxide or nitride layer is required at the interface, Si surfaces prepared by an HF last clean show a long incubation time and lead to inferior film quality[10].

Naturally, leakage current and dielectric film thickness are directly related. Figure 9 shows a plot of leakage current versus capacitance equivalent thickness (CET) for a series of Al2O3 films of various thicknesses. The exponential dependence of leakage current on CET is clearly visible. The high-k film thickness has to be chosen such that the leakage current specification of < 1 fA/cell is met.

Figure 9. Leakage current versus capacitance equivalent thickness for Al2O3 films of various thicknesses in 110nm ground rule trench capacitors.

Integration of Metal into Trench DRAM Capacitors

Metal electrodes or metal fills are anticipated for ¯ 70 nm ground rules. A metal fill would significantly reduce series resistance of the inner electrode of a trench capacitor. The use of a metal electrode would eliminate the poly silicon depletion effect and help to further reduce CET. Thermal stability of the metal in contact with adjacent layers is crucial.

The integrity of a TiN/Poly-Si/NO/Si MSIS structure upon annealing was investigated. The TiN layer was deposited by ALD on top of a thin poly-Si buffer layer which is in direct contact with the NO dielectric layer inside a high aspect ratio trench. This MSIS trench structure was subjected to various post anneals. Both capacitance and leakage current remained stable even after annealing at 1000°C demonstrating the high thermal integrity of the TiN MSIS material system. Small resistivity values of < 100 µOhmcm were observed after high temperature annealing. 80 % step coverage was achieved for 20 nm TiN deposited by ALD into trenches with AR > 40. This is in perfect agreement with the metal fill requirements for trench DRAM. 70-80% step coverage is adequate to guarantee sufficiently low series resistance down to the bottom of the trench.

ALD Equipment Issues

ALD equipment is now being adopted by the semiconductor industry for a number of applications. ALD system maturity has been advanced significantly in recent years. Commercially available systems at Infineon have shown good overall process repeatability, excellent thickness uniformity, low particle counts, and reasonable throughput. Nonetheless, there are areas which require improvement. The number of wafers between cleans has to be increased. Likewise, the chamber cleaning procedures need to be optimized. Ideally, in-situ cleaning capability for ALD chambers should be made available. However, isotropic removal of materials such as Al2O3 and HfO2 from the reactor walls may not be straightforward and needs to be studied in detail.

Summary

Atomic Layer Deposition is gaining increasing momentum in the semiconductor industry. ALD offers significant advantages over conventional deposition processes with respect to step coverage, uniformity, film thickness control, and film quality.

Infineon is actively pursuing ALD for a number of applications, among them high-k dielectric and metal electrode deposition for DRAM storage capacitors. For the first time, fully functional 128 Mb DRAM chips with ALD Al2O3 trench capacitors have successfully been fabricated in 170nm technology. The excellent step coverage control achieved with ALD will be an essential asset as trench capacitors are scaled to ever smaller dimensions and higher aspect ratios.

References

[1] P.D. Agnello, Process requirements for continued scaling of CMOS – the need and prospects for atomic-level manipulation, IBM J. Res. & Dev., 46 (2002) 317

[2] H. Seidl et al., A fully integrated Al2O3 trench capacitor DRAM for sub-100nm technology, IEDM (2002)

[3] Mikko Ritala and Markku Leskela, Atomic Layer Deposition, Handbook of Thin Film Materials, vol. 1: Deposition and Processing of Thin Films, ed. H.S. Nalwa (2002) 103

[4] A.W. Ott et al., Al2O3 thin film growth on Si(100) using binary reaction sequence chemistry, Thin Solid Films 292 (1997) 135

[5] O. Sneh et al., Thin film atomic layer deposition equipment for semiconductor processing, Thin Solid Films 402 (2002) 248

[6] G.D. Wilk et al., High-k gate dielectrics: Current status and materials properties considerations, J. Appl. Phys. 89 (2001) 5243

[7] M. Gutsche et al., Capacitance enhancement techniques for sub-100nm trench DRAMs, IEDM (2001) 411

[8] J.-H. Lee et al., Practical next generation solution for stand-alone and embedded DRAM capacitor, VLSI (2002) 114

[9] U. Schroeder et al., Experimental
and theoretical investigation of ALD
step coverage in high aspect ratio trenches, AVS ALD Conference 2002, Seoul

[10] H. Bender et al., Physical characterization of high-k gate stacks deposited on HF-last surfaces, IWGI (2001) 86

Biographies

Martin Gutsche

Dr Martin Gutsche is Senior Staff Engineer and Project Manager for advanced high-k materials development at Infineon Technologies in Munich, Germany. Since joining Siemens in 1996, Martin has held various positions in the area of process and materials research and development. From 1996 to 1998, he worked on plasma etching for advanced semiconductor applications in the joint IBM-Siemens DRAM Development Alliance in Hopewell Junction, NY. Since returning to Munich in 1998, his focus has been on techniques to enhance capacitance in DRAM capacitors. Martin initiated ALD work at Infineon and has substantially contributed to the high-k development program. Recently, he has also become involved in ITRS roadmap work. Martin received a doctorate in Physics in 1995 from the Technical University of Munich, Germany. He is an author or co-author of more than 20 technical papers and holds more than 10 U.S. patents.

Harald Seidl

Harald Seidl is Senior Staff Engineer and Project Manager for metal electrode materials development at Infineon Technologies in Munich, Germany. He received his MSc in Physics in 1993 form the University of Munich, Germany. In 1994 he joined Hitachi Semiconductor Europe in Landshut, Germany, where he held positions in process engineering and engineering management. After joining Infineon Technologies in 1999 he worked as Project Manager for high-k development in Dresden, where he introduced ALD and high-k materials into the development line. Since moving to Munich in 2001, his focus changed to metal electrode materials for DRAM applications. He is an author or co-author of several technical papers in the field of semiconductor industry and film deposition.

Thomas Hecht

Dr Thomas Hecht is working on integration
of high-k materials in the Memory Products division at Infineon Technologies Dresden. He joined Infineon Technologies in 2000
and specialized in ALD deposition and integration aspects of high-k dielectrics. Thomas worked in 1996 at Arizona State University and received his doctorate
degree in physics in 2000 at the Humboldt-University Berlin, Germany. He is author
or co-author of more than 15 publications
in surface science and semiconductor processing.

Stephan Kudelka

Stephan Kudelka is Senior Engineer of the DRAM Innovation Projects group for Infineon Technologies in Dresden, Germany. In 1997 he joined Infineon (formerly Siemens Mircroelectronics) in the DRAM Development Alliance with IBM and Toshiba, NY, where he worked on research and development for advanced wet cleaning and etch processes. He introduced a novel Si etch process to enhance the capacitance of DRAM capacitors for future generations. From 1999-2001 he worked on the integration of vertical device trench DRAM cells. Since he returned to Germany in 2001, he has focused on the integration of high K dielectrics and metal electrodes in capacitors for DRAM applications. He received his doctoral degree in Physical Chemistry from the University of Düseldorf, Germany and contributed more than 20 technical papers and more than 10 U.S. patents.

Uwe Schroeder

Dr Uwe Schroeder is Project Manager for High-k Development in Memory Products at Infineon Technologies in Dresden. He received his doctoral degree at University of Bonn, Germany including a research visit at UC California, Berkeley and worked at University of Chicago as a post-doctoral researcher. He joined Infineon formerly Siemens Semiconductor for DRAM development in the DRAM Development Alliance with IBM and Toshiba in Hopewell Jct., NY before transferring to Infineon’s Memory Development Center in Dresden, Germany. Currently, he works on ALD process development and integration into memory products. Dr Schroeder has contributed over 15 publications in the field of semiconductor industry and film deposition.

Contacts

M. Gutsche, H. Seidl
Infineon Technologies
Balanstrasse 73
81617 Munich
Germany
Tel: +49-89-234-46619
Fax: +49-89-234-955-4288

E-mail: martin.gutsche@infineon.com

T. Hecht, S. Kudelka, U. Schroeder
Infineon Technologies
Koenigsbrueckerstrasse 180
01099 Dresden,
Germany

 
 
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