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Developing a WSix Gate Etch Process with CD Bias Uniformity less than 3 nm
(2/3/2004) Future Fab Intl. Issue 16
By Wilfred Pau, Applied Materials
Meihua Shen, Applied Materials
Shashank Deshmukh, Applied Materials
Takanori Nishizawa, Applied Materials
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Shrinking device geometry and differing material properties pose challenges for the gate etch process at 130 nm and below. A 300 mm hardmask (HM) WSix gate etch process is developed that achieves the desired WSix and poly profiles, good selectivity to the HM, and CD bias uniformity of < 3 nm (3). A CF4/Cl2/N2 chemistry main etch (ME) etches the Wsix layer to endpoint plus a certain over-etch percentage. The remaining poly film is etched with a HBr/Cl2/HeO2 chemistry soft-landing (SL) step until the poly layer starts to clear. Poly residue is removed using a HBr/HeO2/He over etch (OE). The eff

Critical dimension (CD) bias uniformity of < 3 nm is commonly required for gate lengths of approximately 130 nm with a 1- to-1 line-to-space (LS) ratio. Yet as the LS ratio approaches 1, it becomes extremely difficult to minimize profile microloading between dense and isolated lines. Other challenges include HM selectivity, profile loading, selectivity to gate oxide, and CD bias uniformity.

Welcome to Future Fab Vol. 15

Introduction

As a manufacturer of specialty materials, POCOs materials research and development teams are constantly Introduction In advanced DRAM manufacturing, gate length and spacing continue to shrink while performance requirements become more stringent. Film stack composition imposes additional complexity, because the film stack consists of two different materials. Polycide (tungsten silicide [WSix] on poly) is currently the mainstream gate electrode material in DRAM fabrication, while tungsten (W) on poly or directly on gate oxide are targeted for next-generation technology. WSix and W are favored, because their low resistivity reduces the resistive current delay of the gate transistor, thereby increasing device speed.

Critical dimension (CD) bias uniformity of < 3 nm is commonly required for gate lengths of approximately 130 nm with a 1- to-1 line-to-space (LS) ratio. Yet as the LS ratio approaches 1, it becomes extremely difficult to minimize profile microloading between dense and isolated lines. Other challenges include HM selectivity, profile loading, selectivity to gate oxide, and CD bias uniformity.

To maximize HM selectivity, CF4 flow and bias power must be decreased in the WSix ME. To clear all WSix, a so-called overetch step (WSix OE) is introduced. To minimize profile microloading, the WSix OE percentage must be high enough that, after the OE, the WSix profile on dense lines is not too tapered compared to that on isolated lines. In turn, CD bias uniformity improves as profile microloading between dense and isolated lines decreases and profile loading improves. These issues were addressed in developing a process that produced the requisite profile and selectivities to achieve CD bias uniformity of < 3 nm (3).

Development Methodology

A baseline process was established on 200 mm wafers to achieve good WSix and poly profile, and CD bias uniformity of < 3 nm (3). This process was then scaled up and fine-tuned to achieve the same performance on 300 mm wafers. The work was performed using a high conductance polysilicon etch chamber equipped with a dual-coil, tunable plasma source and advanced gas distribution system. The former facilitates control of plasma density uniformity. The latter permits control of pressure and gas flow throughout the chamber to adjust distribution of etchants and their byproducts and, thereby, influence etch rate behavior.

200 mm Process Development

The process required a uniform CD bias across the wafer, high selectivity to the nitride HM, and a slightly tapered WSix profile, the latter to be rendered vertical by a subsequent wet clean process. The initial process produced a vertical WSix profile and tapered poly profile, CD bias uniformity of approximately 5 nm (3), and insufficient HM selectivity. The HM selectivity and WSix profile were optimized using process chemistry, total flow, and source and bias power levels.

HM selectivity is most affected by changes in CF4 flow and bias power in the WSix ME step as these two parameters have the greatest effect on the HM etch rate. Figure 1 shows the effect of reducing CF4 flow. HM remaining improved by 5 percent, but the WSix profile also became more tapered. Three parameters were adjusted in an attempt to produce a more vertical profile. First the total flow and ratio of source power to bias power were increased.

However, the profile became too undercut (Figure 2). Increasing N2 flow resolved the problem by providing sidewall passivation without affecting HM selectivity. As can be seen in Figure 3, reducing the ratio of source power to bias power and increasing N2 flow produced a vertical WSix profile and good HM selectivity. The final 200 mm process resulted in good WSix and poly profiles with > 2000A HM remaining and CD bias uniformity of < 3 nm (3) (Figure 4).

300 mm Process Development

Using a known methodology, the 200 mm process was scaled to serve as the starting recipe for 300 mm development. The scaling maintained pressure and gas flow, but increased source power by approximately 30 percent and bias power by 50 to 60 percent for the ME and SL steps. Because the OE could not scale up directly, the baseline process for the 300 mm chamber was used.

This phase of development emphasized gate oxide selectivity in the SL step, improved poly profile loading, and CD bias tuning. Originally, the SL step had a threesecond extension after endpoint to remedy a tapered poly profile. However, the thickness of gate oxide remaining measured at the low end of the specified range. The extension was therefore eliminated, but the SL step itself needed fine-tuning to avoid increased tapering of the HeO2-sensitive poly profile. Higher HeO2 flow improved gate oxide selectivity but produced more tapered profiles. Substantially increasing the flow of Cl2, however, restored the vertical profile (Figure 5).

The primary cause of CD nonuniformity is profile microloading between center and edge of the wafer. Typical poly SL and OE steps result in profiles that are more vertical at the center of the wafer than at the edge. To minimize this profile loading, the poly etch rate non-uniformity for all three steps had to be optimized. In the DPS II poly etcher, etch rate nonuniformity can be easily tuned. The dualcoil source power supply allows independent control of RF power to each coil, enabling uniform RF power deposition on the wafer under a wide range of process conditions. By adjusting the coil ratio (outer coil current to inner coil current) plasma uniformity can be adjusted. Using the tunable gas nozzle, relative gas flows to the center and edge of wafer can be adjusted to control byproduct distribution and, hence, relative etch rates and passivation.

Increasing the coil ratio and reducing the TGN ratio (volume of outer to inner flow), improved ME etch rate nonuniformity from 5 percent (1) to 2.5 percent (1) (Figure 6). To optimize OE etch rate non-uniformity, helium flow was increased to reduce the etch rate at the wafer center. However, this created slightly tapered poly profiles at both center and edge of the wafer, although less so at the center (Figure 6). Optimizing the SL etch rate non-uniformity remedied this effect. Typically, the SL etch rate pattern is slow at the center and edge of the wafer and fast in the area between. Because the profile was more tapered at the wafers edge, the process was tuned to etch faster there. Coil ratio was raised and the TGN ratio in the SL step reduced to create a center slow, edge fast pattern that produced vertical poly profiles at both center and edge. Once profile microloading was minimized, CD bias uniformity improved. Figure 7 shows CD bias and uniformity across the wafer before and after etch rate optimization. Before optimization, CD bias trended upward towards the edge of wafer and uniformity was approximately 5 nm (3). After optimization, the CD bias trend became more random, CD bias uniformity improved to less than 3 nm (3), and dense/iso CD microloading also improved.

 

CD Bias Tuning

CD bias could be adjusted by modifying the WSix and/or poly profile through both the ME and SL. In the ME, profile hence CD bias was most sensitive to N2 flow (Figure 8a). Alternatively, pressure, source power, bias power, and HeO2 flow in the SL could influence CD bias (Figure 8b). The percentage OE after the WSix ME step also affected CD bias. CD loss grew with the OE percentage (Figure 8c), changing by more than 7 nm as OE percentage increased from 30 to 40 percent. This was because the taper remaining in the WSix profile after ME endpoint, especially in the dense area, was eliminated during the OE. Poly film is also etched during WSix OE. Therefore, the amount of poly remaining after WSix OE also depends on the OE percentage. The more poly remaining, the longer it takes to reach SL endpoint. In this work, SL endpoint time of approximately 16 seconds yielded optimal profile and CD bias.

Conclusion

By fine-tuning the ME, SL, and OE steps, an HM polycide gate etch process was developed to etch polycide gate wafers for advanced DRAM fabrication at 130 nm and below. The process produced good HM and gate oxide selectivities, and the requisite slightly tapered WSix profiles, good vertical poly profiles, and CD bias uniformity of < 3 nm (3) (Figure 9). The WSix was etched with CF4/Cl2/N2 chemistry to endpoint plus an OE percentage; remaining poly film was etched to endpoint with a HBr/Cl2/HeO2 SL step. Poly residue was removed with a high-selectivity HBr/HeO2/He OE.

 

 

 

 
 
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