A red brick wall is looming in the Interconnect chapter of the International Technology Roadmap for Semiconductors (ITRS), a barrier caused by the difficulty integrating porous low-k dielectrics, combined with the rising resistivity of the copper interconnect system. As consumers demand more functionality in smaller spaces, the industry is considering interconnect as a possible solution to the copper-low-k conundrum. Just as spacechallenged architects sparked the skyscraper boom in the early 1900s, chip designers may look to the third dimension now that chip real estate is at a premium. But will a 3D architecture be costeffective? What must we do to understand the potential benefits and pitfalls? When the analysis is complete, will Interconnect be the next great thing – just a niche technology? This article addresses these and other questions about one of our industry’s hottest emerging technologies.

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