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SRAM – The Path to FinFET Manufacturing
(7/9/2007) Future Fab Intl. Issue 23
By Chenming Calvin Hu, University of California, Berkeley
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FinFET[1] allows the gate to control the channel from several sides (see Figure 2), thus increasing the gate control and allowing the gate length to be reduced further. Since the introduction of FinFET, this structure has been used to set new world records of the smallest gate length several times at various research laboratories.

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Using embedded SRAM as a path, FinFET should enter manufacturing at 32nm, significantly earlier than some experts expected. FinFET provides several advantages over the planar MOSFET structure – smaller size, larger current, smaller leakage and less variation in threshold voltage. The difficulties of implementing it into mass production are the risks of treading new grounds and the need to get design tools and circuits developed at the same time as the manufacturing technology. Embedded SRAM cells provide an ideal vehicle for the initial deployment of FinFET because it can benefit more from FinFET than logic circuits initially and does not require extensive design tool and circuit development.

Advantages of FinFET Over Planar MOSFET

What makes a transistor different from a resistor is that the gate controls the conduction channel, not the drain. The gate exerts its control through capacitive (electrostatic) coupling to the channel. When we shrink the MOSFET gate to a smaller size, the drain is pulled closer to the (middle of the) channel. That increases the capacitive coupling between the drain and the channel (see Figure 1). When the gate is too small, the gate no longer has the dominant control of the channel, and current (leakage current) can flow just because a drain voltage is applied, even without the help of a gate voltage. This is the problem faced by the planar transistor. It is being dealt with by heavily doping the channel. Unfortunately there are significant side effects in the form of low carrier mobility due to carrier scattering and Vt variation due to random dopant fluctuation.

FinFET[1] allows the gate to control the channel from several sides (see Figure 2), thus increasing the gate control and allowing the gate length to be reduced further. Since the introduction of FinFET, this structure has been used to set new world records of the smallest gate length several times at various research laboratories. The current record for the smallest gate length is 3nm. Clearly, FinFET can serve many technology nodes.

Barriers Between FinFET and Manufacturing – Contrast With High-k/Metal-Gate Technology

It is useful to contrast the challenges of implementing high-k/metal-gate with the challenges faced by FinFET. The former is also a breakthrough technology. It is arguably a significantly more difficult technology than FinFET because new materials and a host of complex issues of materials, surface chemistry, work-function physics and engineering, and reliability are involved. Take the reliability risk for example. The SiO2 gate dielectrics started at 200nm thickness 40 years ago and got thinned down ever so gradually and carefully at each technology node to the point where it cannot be thinned any more. Although the material remained the same, at each incremental thinning, a significant amount of reliability testing was conducted and the concern for reliability failures was always there. We are basically using 40 years of reliability experience to guarantee the 10-year lifetime of SiO2. The new high-k dielectric has not had the benefit of gradual improvement. It is an amazing engineering feat to introduce it at a more aggressive “equivalent thickness” than SiO2 and commit it to production with implied assurance of 10 years of reliability.

However, high-k/metal-gate has an advantage over FinFET. There is no change in transistor layout. It is a drop-in replacement for SiO2 in that sense and needs no change in the SPICE model, layout tools, digital and analog cell libraries, reusable circuit blocks, and place and rout. However, replacing all the transistors in a complex IC with FinFETs would require cross-function and cross-company co-development of manufacturing and design technologies. That is a tall additional barrier for the introduction of FinFET. Fortunately, there is an easier way to introduce FinFET into production.

A Compelling Case for FinFET in Embedded SRAM

FinFETs can coexist with planar MOSFETs in a conventional CMOS process with minimal additional process steps. By laying out two shallow-trenchisolations (STI) close together, we can create a silicon “fin” surrounded by STI oxide. The depth of the STI is around 200nm. Using an additional mask to recess the STI oxide by perhaps 40nm, we can expose a 40nm tall fin ready to be processed into FinFET by going through the rest of the standard CMOS process flow. Making FinFETs this way has been demonstrated by Samsung, TSMC, Intel and Toshiba. It is important to note that during the same process flow, conventional planar transistors can be also produced side by side on the same chip as the FinFETs. The fin height of the FinFETs is kept small, and is chosen to minimize the need for adjustments of the lithography, etching and highk dielectric deposition process modules.

Since FinFETs and planar transistors coexist, it is not necessary to replace the planar transistors in the logic and analog circuits with FinFETs. Instead we can use FinFETs in only the SRAM cells. SRAM cells are handcrafted and are designed with resources available within the technology development team of a semiconductor company. In fact, SRAM is the standard process technology development vehicle. Verification of the yield and performance of the SRAM is part of the deliverables of the technology development effort. By the time the technology development program is finished, the embedded FinFET SRAM is ready to be included in product designs.

Fortuitously, embedded SRAM alone is more than enough to justify the investment in FinFET development because SRAM can take up most of the chip areas in some IC products and designers are scrambling to reduce the cell size. In addition, SRAM is in greater need for help from a newer transistor than logic circuits. Many designers consider SRAM the greatest design challenge at 45nm because it is sensitive to leakage, Vt variation and drive current.

FinFET is perfect for reducing size and leakage because of the better gate control over the channel. It can also deliver greater current because the multiple surfaces that conduct current provide a larger channel width than the planar transistor. A more subtle reason is the higher carrier mobility due to the elimination of heavy channel doping (necessary in planar transistors to suppress drain leakage current). A lightly doped channel eliminates impurity scattering. It also reduces surface scattering because the electric field that pushes the carriers to the surface is weaker. Finally, when the channel doping concentration is very low, there is no significant number of dopants to be found and therefore no dopant-fluctuation- induced Vt variation.

It has been shown[2] that 45nm-node SRAM noise margin can be increased from 135mV to 175mV while the cell size is reduced by 20 percent when FinFETs replace the planar transistors (Figure 3a). If an additional process step is taken to give each fin two separate gates, the noise margin improves further to 300mV (Figure 3b).

Beyond SRAM

SRAM is not the only path to FinFET manufacturing. Memory in general shares the ease of introducing FinFETs, heightened needs for smaller size and/or sensitivity to leakage. Both DRAM and Flash memories are attractive products for FinFET deployment.

Still, embedded SRAM is a particularly important path to FinFET manufacturing because it will lead to the spread of FinFET technology for logic and analog circuits. The spread from SRAM to logic should take only one technology node. To help enable the use of FinFETs in memory, logic and analog circuit designs, a SPICE model fashioned after the popular international standard SPICE model of planar transistors, BSIM, has been developed and verified on FinFET fabricated, with the planar CMOS technology.[3]


  1. X. Huang et al., “Sub-50nm FinFET: PMOS,” 1999 IEDM, p. 67.
  2. Z. Guo et al., “FinFET-based SRAM design,” International Symp. Low Power Electronics and Design, August 2005.
  3. M. Dunga et al., “BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design,” 2007 VLSI Technology Symposium.

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