Introduction

CMOS scaling as we approach the 22nm node and beyond has turned to new devices and materials as a means to keep the performance gains and physical device shrinks at a constant historical pace. This has included the use of alternate channel materials with higher mobility such as SiGe, Ge and III-V materials as well as alternate structures such as FinFETs and tri-gate transistors.[1,2] While the alternate channel materials do offer a significant increase in device current, the issues with fabrication of practical devices such as temperature stability, gate dielectric, off-state leakage and parasitic capacitance need workable solutions. Alternate device structures such as FinFETs offer a means of packing more current (and thus more speed) per unit area onto a chip while keeping the processing, materials and circuit design factors relatively consistent with previous technology nodes.[3,4] The benefits of such a shift in the device structure come from several factors that are improved in FinFETs: reduced device variability arising from random dopant fluctuations, reduction of short-channel effects by the implementation of multiple gates and improved volume inversion of the channel region.[5,6] While FinFETs have shown high drive currents with known processing methods, serious challenges still confront the final implementation of FinFETS in highly scaled circuits such as SRAM and high performance logic. In this report we outline some of the critical issues that still confront the introduction of FinFETs in product.

The most serious of roadblocks to scaling that have pushed device engineers to consider radical changes in the device architecture is the gate scaling.[7] In order for the device to accommodate ever-shorter channel lengths, the dielectric thickness also has to be reduced for electrostatic reasons. The introduction of high k and metal gates at 45nm have improved the fringing gate capacitance problem so that we can continue scaling, but even the incremental gains from high k gate dielectric may not be enough by the 22nm node to allow < 20nm gate lengths.

The control of channel carriers from two directions, as the FinFET provides, improves device parameters such as sub-threshold slope, and reduces short-channel effects such as drain-induced barrier lowering. The progress in the formation, control and integration of FinFETs has progressed well over the past seven years,[8-10] but significant roadblocks are still in place that prevent the complete utilization of FinFETs as of yet, as outlined in the next few sections. Furthermore the use of a multiple gate transistor should have extendibility beyond one technology generation, indicating that FinFETs may need to be compatible with many of the performance-boosting elements used today such as strain engineering, but with alternate channel materials as well.

The FinFET Structure

Simply described, the FinFET is an ultrathin-body SOI device turned on end with another gate placed at the back (see Figure 1a). Issues that arise with the formation of this structure alone include spacer formation on the gate only[11] (removal of spacer from the fin structure while maintaining fin integrity), spacer thickness and gate etching. The attraction of the FinFET device is utilization of standard process techniques that are already common in CMOS manufacturing. One caveat is the fin lithography itself. In using fins for the 22nm node, the fin thickness will need to approach < 10nm controllably with low line edge roughness and line width roughness. The reason for this fin thickness criterion comes from electrostatic modeling. The channel region of the fin must be in complete inversion to eliminate severe short-channel effects. This can only be achieved when the width of the fin is roughly half the gate length. The most popular proposed solution to achieve such thin fin widths is a spacer transfer technique.[12] This method of highly dense, ultrathin fin formation may require novel device and circuit integration techniques, but the promise of manufacturable fins exists. One other aspect of the FinFET structure is the need for compatible advanced high k/metal gate (HKMG) deposition techniques. With recent announcements on the use of HKMG as early as the 45nm node, its extendibility beyond a single technology node is critical. Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are fully conformal processes, making them compliant with the 3D nature of the FinFET when the gate stack is deposited and extending HKMG beyond 32nm node if FinFETs are used. FinFETs must also be compatible with stress techniques that have been in place for several technology nodes, but recent reports indicate that stress on fin does achieve performance enhancement.[13]

Contact formation is critical in reducing series resistance of a FinFET device given the 3D structure of the fin and the need to achieve the current density as outlined in the previous section. There are two ways of making contacts that have individual pros and cons. The formation of a contact directly on the fin source/drain (S/D) itself as in Figure 1b can be scaled to higher densities since the fin footprint is minimized, but it requires novel techniques for fin doping (due to the reduced capture cross section of the fin during implantation), S/D epitaxy and silicidation to reduce the series resistance. Conversely, the addition of a pad for contact in Figure 1b can improve contact issues. As is readily apparent, this structure has poor area dedication, negating some of the density benefits of the FinFET device, but we have better understanding of low contact resistance and doping of a larger planar pad area, giving better opportunities for high device performance.

Area Scaling of FinFETs

In the engineering analysis of the usefulness of FinFETs, a fair comparison of the overall current density as a function of chip area must be made. Simply put, at what fin dimensions and density do we actually get an improvement in the amount of current per unit area of the chip? If we cannot exceed current device drive values by an appropriate scaling margin, then the FinFET is not as attractive given the added process complexity. The geometry of the fin makes the benefit analysis difficult, but we can make some simple assumptions to understand where the device is attractive.

The reference device is a comparable area planar device. This is illustrated in the plan view in the inset of Figure 2. The planar device has a width W, while the effective channel width WEff of an individual fin is 2 times the fin height HFin. Assuming the contact issues (to be discussed forthwith) have been solved to the point that the FinFETs operate with IDrain /(2*HFin)=1 mA/µm with 10nm fins, and assuming the active width of the two devices are similar in the direction normal to W, we can calculate the current per-unit length in the W direction of the FinFETs versus the spacing and height of the fins. The results are shown in Figure 3. We can see that in order to meet a ~2 mA/µm criterion needed for 22nm node,[14] the fin spacing for an 80nm-tall fin is about 70nm, or roughly equal to the fin height. This is an aggressive goal and is further exacerbated by the need to maintain low series resistance. Logically, the required density increases (required fin spacing decreases) as the fin height is decreased.

As previously discussed, we wish to make contact, for aerial reasons, to a fin without the need for a pad area. One issue that arises in the silicidation of a 3D object is the multiple facets available for Ni diffusion. This is highlighted in the top row of Figure 3. Ni is deposited over a fin, and then annealed to diffuse the Ni into the fin. The remaining un-reacted Ni is then stripped. The progression of figures shows that even with the small amount of initial 50 Å Ni deposition, > 60 percent of the fin is consumed with the entire top portion of the fin fully silicided. As the thickness is increased to 150 Å, the full fin is silicided. Since the images are a good representation of the silicide profile as the fin enters the spacer (see Figure 1), then the contact resistance of the silicide to the fin will dominate, thereby increasing series resistance. Thus we see that additional Si in the form of selective Si epitaxy must be added to the S/D region to prevent the full silicidation of the fin.

Epitaxial growth of Si to enhance the fin thickness should be low temperature to prevent agglomeration of the fin, planar area should be added to the fin for contact and should provide an optimized cross section for the correct silicide profile. Figures 3b and 3c depict CVD epitaxy on fins without and with merging of the fins, respectively. The merged fins will have higher series resistance due to the spreading resistance of the doped S/D, but the unmerged fins may have higher contact resistance. The balance of maximized silicide/Si area and reduced S/D must be optimized to achieve the lowest possible series resistance.

Extendibility of FinFETs

One excellent benefit of the FinFET devices that could help its extendibility into further technology nodes is extreme height scaling. If the starting material is carefully controlled, the resulting fins are in reality nanowires with dimensions interesting in quantum mechanical realm.[15] This is shown Figure 4a. The starting Si was thinned to < 6nm and spacer transfer process applied to form fins. With controlled post-fin processing, double nanowires of Si are formed. These can then be further processed to make nanowire transistors and optical Si devices. The benefits of such a device must be further explored, but with the experience gained in the manufacturing of FinFETs these questions will naturally be addressed in the future.

As mentioned previously, FinFETs may need to extend to new channel material to allow utilization beyond one technology generation. To this end, SEMATECH is also examining the effect of SiGe and Ge as the fin channel in PMOS FinFET devices. Figure 4b shows the cross section TEM of a standard Si channel where epitaxial Si has been grown on the fin sidewalls. The bottom oxide has been purposefully undercut to form a multiple channel device. Note the excellent uniformity of the gate dielectric and metal, underscoring the extendibility of HKMG ALD processes as mentioned previously. Figure 4c shows the TEM of a similar device but with SiGe grown as the channel material on the fin sidewall. As can be seen in the IDrain-VGate curve in the inset, there is a significant boost in saturation current for the SiGe PMOS device. The results demonstrate the possibility of alternate channel material in a FinFET device.

Unit Processes in FinFET devices

Introduction of metal gates for conventional planar devices requires that distinct band-edge dual work function metals be employed for attaining n and PMOS work functions, with the added complexity of integration of two distinct metals.[16,17] However, these may require particular integration approaches that isolate metals in the NMOS and PMOS regions. Similar problems exist for FinFET devices but with slightly relaxed work function requirements on the metals. Figure 5 indicates that with special processing conditions, the correct metals can be isolated to the appropriate regions on the same wafer. Furthermore the resultant devices have symmetric operation with excellent short-channel device characteristics. These results and the specific process integration details will be chronicled in a future publication.

Conclusion

The challenges of FinFET devices are not limited to the simple formation of the fin, gate and spacer. Attention must be paid to the inter-optimization of the S/D silicidation, epitaxial process, pitch and fin height. While the pitch of fins must be aggressively scaled, opportunities for fabricating FinFETs that surpass planar devices in raw current per unit area in chip real estate do exist. Finally, our results indicate the feasibility of extending FinFETs with HKMG processes as well as alternate channel materials and nanowires.

References

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About the Authors

H. Rusty Harris

H. Rusty Harris earned a B.S. in engineering physics (’97) and an MSEE (’99) from Texas Tech University. He received a Ph.D. in electrical engineering from Texas Tech University (’03) in the area of surface and interface analysis for silicon devices. He initiated the design and construction of a $1.9 million semiconductor lab at the University of Missouri-Columbia while teaching undergraduate classes as a visiting assistant professor. Dr. Harris is currently the manager of Non-Planar CMOS Extension as an Assignee to SEMATECH in Austin, Texas.

Muhammad Mustafa Hussain

Muhammad Mustafa Hussain is an integration engineer with the Front End Processes Division of SEMATECH. He has authored more than 30 technical papers in industry peer-reviewed journals, and has developed numerous patent applications. Dr. Hussain holds a Ph.D. in electrical engineering and a master’s degree in electrical engineering (solid state electronics) from The University of Texas at Austin; a master’s in electrical engineering from the University of Southern California; and a bachelor’s degree in electrical engineering from Bangladesh University of Engineering and Technology.

Casey Smith

Casey Smith is a Ph.D. candidate in materials science from the University of North Texas. He is currently an intern in the Non-Planar CMOS Extension at SEMATECH. His research focuses on materials and processing to reduce RC delay for front/back-end semiconductor manufacture.

Ji-Woon Yang

Ji-Woon Yang received his Ph.D. degree from the University of Florida, Gainesville, in 2004. Since 2005, he has been with the FEP division, SEMATECH Inc., in Austin, Texas. His research interests include the characterization, analysis and simulation of high-scaled CMOS technology.

Prashant Majhi

Prashant Majhi received his doctorate in science and engineering of materials from Arizona State University, and his bachelor’s degree in metallurgical engineering from the Indian Institute of Technology in Madras, India. He has worked at Philips Semiconductors since 2001, leading projects in advanced BiCMOS processes and advanced high-k dielectric process development and integration. Dr. Majhi currently is assigned to SEMATECH as a project manager working in advanced gate electrodes.

Hemant Adhikari

Hemant Adhikari received his M.S. in management science and engineering in 2006 and his Ph.D. in materials science and engineering in 2007, both from Stanford University. Currently he is an AMD assignee at SEMATECH working with the Front End Processes group.

Hsing-Huang Tseng

Hsing-Huang Tseng received a Ph.D. in materials research from Princeton University. He joined the Advanced Products Research and Development Laboratory (APRDL) of Motorola in 1985. He has been responsible for process and integration development for a variety of gate dielectrics for advanced technologies. There he becamse a Distinguished Member of Technical Staff and a Motorola Master Innovator, with 25 issued U.S. patents. He currently serves as Chief Technologist and CMOS Extension Program Manager of the Front End Processes Division at SEMATECH and has authored or co-authored more than 70 papers for professional journals and conferences.

Raj Jammy

Raj Jammy holds a doctoral degree in electrical engineering from Northwestern University. Upon graduation, he joined IBM’s Semiconductor Research and Development Center in East Fishkill, N.Y., where he worked on front-end technologies for deep-trench DRAMs. He subsequently became manager of the Thermal Processes and Surface Preparation group in the DRAM development organization. In 2002, Dr. Jammy moved to T. J. Watson Research Center in Yorktown Heights, N.Y., to manage IBM’s efforts in high-k gate dielectrics and metal gates. In 2005, he accepted assignment to SEMATECH as director of its Front End Processes Division. He holds more than 50 patents and is an author/co-author of over 75 publications/presentations.