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Impact of Wafer-Level 3D Stacking on the Yield of ICs
(7/9/2007) Future Fab Intl. Issue 23
By Robert Patti, Tezzaron Semiconductor
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To take advantage of process separation, a 3D DRAM chip would be designed with all its bit cells on separate layers from its support circuitry. The processing of the two types of layers, on their separate wafers, would be very different – each process highly optimized for its contents.

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Semiconductor manufacturing is all about yield. Today 3D-ICs are a hot topic, but manufacturers need to know how 3D will impact their yield percentages. This chapter seeks to investigate the issue from several angles.

It must be noted that there are several wafer stacking methods in use today. Wafer bonding can be done with thermal compression, or adhesives or molecular bonds. Temperatures and alignment tolerances differ. The types of wafers that can be stacked, the number of levels, the final thickness of the stack, the density of vertical interconnect – all these features vary widely among the different methods. Clearly the yields must vary as well, but most yield numbers are not published for these new and proprietary processes. Therefore, this chapter discusses the factors that are generally shared among all methods and points to those areas where stacking methods can be expected to differ.

The Basics of Wafer-Level 3D

In order to understand how it affects yield, we need to understand how wafer-level 3D is accomplished:

  • First, the circuit design is engineered to fit on separate layers, all exactly the same size.
  • Next, the layers are manufactured separately, on separate wafers.
  • Third, the wafers are aligned, stacked and thinned.
  • Last, the wafer stacks are diced into individual devices.
  • Somewhere in the process, vertical vias are incorporated into the devices
  • either in a “via-first” manner, building the vias into the wafer circuitry before stacking, or in a “via-last” process, creating vias after each wafer bond.

An important factor in wafer-level 3D is process separation. If the stacking me-thod allows a high density of vertical interconnect, the designer can divide the components of an IC onto separate layers according to their process requirements. The process for each layer can then be optimized for its components. As an example, let’s take DRAM memory, which contains elements with very different characteristics. Table 1 separates the elements into two categories based on their process requirements.

To take advantage of process separation, a 3D DRAM chip would be designed with all its bit cells on separate layers from its support circuitry. The processing of the two types of layers, on their separate wafers, would be very different – each process highly optimized for its contents.

Standard Yield Factors

Some of the factors generally recognized to affect yield are die area, circuit density, the number of mask steps and the maturity of the process. Let’s look at how these are affected by 3D:

Die Area
A larger die has a greater likelihood of containing a “killer” defect. 3D does not change this: If a 400 mm2 design is divided into four 100 mm2 layers, it contains the same silicon area and therefore has the same probability of a killer defect.

However, a larger die also results in fewer die sites per wafer and more wasted silicon along the wafer’s rim. In this respect, 3D is very helpful: The several layers are built as several small dies rather than one large one, so the wafer area is used more efficiently with less waste around the edge. This advantage becomes more pronounced for devices with greater total area.

On the other hand, 3D requires vertical vias that take up space, making the die area larger again. The amount of space taken up by vias depends on the number of vias and their cross-section area. The circuit design determines the number of vias implemented, although the stacking method defines an upper limit to their density. Stacking methods also define the cross-section area of each via, with wide variation among current methods.

Circuit Density
Denser circuitry uses silicon more efficiently – a good thing. Denser circuitry also increases the likelihood that any defect on the die will be a “killer” – not so good. Stacked 3D circuits include space for vertical vias, which are high-yield and larger than normal circuit features, so they decrease the density. The bottom line is that vias increase the die area and decrease the density in exactly similar proportions, so the effects cancel very neatly.

Number of Mask Steps
Each mask applied to a wafer increases the chances of error, contamination and breakage. Because 3D design allows process separation, the number of mask steps can often be reduced on individual wafers designed for 3D. Table 2 enumerates the mask steps for our previous DRAM example.

Maturity of Process
Newer manufacturing processes generally suffer lower yield than mature, stable processes. By using 3D, designers can greatly reduce the footprint of an IC without resorting to newer, smaller geometries. Of course, wafer stacking methods are also new processes, with yields (discussed below) expected to increase with maturity.

Specific 3D Yield Factors

In the wafer stacking process, yield issues include extra processing, contamination, alignment, edge effects and design. The impact of these issues is strongly dependent on the method being employed.

Extra Processing
Wafer stacking adds extra steps to the manufacturing process. Any extra handling increases the risk of damage, especially with ultra-thinned wafers. At minimum, all stacking methods must bond each pair of wafers and perform some level of wafer thinning. Via-last methods require additional post-bond processing to create the vias.

Foreign particles caught between the wafers during bonding can cause voids, peeling and delamination. A large “killer” particle causes a large area of void, compromising bond integrity so that the bond fails during subsequent thinning. The result is destruction of the entire layer, or even the whole stack. Smaller particles typically cause localized problems that affect only a single die. The threshold size for a “killer” varies by process; for Tezzaron’s copper-to-copper bonding, the threshold size is about one micron.

In order for the circuitry on the layers to connect properly, the wafers must be precisely aligned for bonding. In via-first processes, this means that the vias built into the two wafers must be placed in contact with one another; for via-last processes, the spaces reserved for vias must align. In general, alignment errors are avoided by making the cross-section of the vias (or reserved via spaces) large enough to compensate for expected variance. Methods that reliably achieve tighter alignments can employ smaller vias. As discussed above, smaller vias allow a higher density of interconnect and a more efficient use of silicon area.

Edge Effects
Regardless of bonding method, the edges of a wafer stack are susceptible to damage. Wafers have beveled edges, so the inter-wafer gap is wider at the edges and the bond is weaker, leaving the bonded edges vulnerable to chipping, peeling and delamination. To improve yield, methods must be employed to strengthen, seal or repair the wafer edges; for example, ragged edges can be smoothed by grinding them.

Chip designs can gain great benefits from 3D implementation. In return, clever designs can provide great benefits to the manufacturing yield. Here are three examples:

  • As mentioned earlier, 3D designers can lay out a circuit so that elements with similar process requirements are on the same layer, allowing highly optimized processing on that wafer. It is reasonable to expect these elements to be more robust and less prone to failure.
  • The design flexibility afforded by 3D can reduce the number of elements needed to perform certain functions. This allows the designer to reduce either the die size or the circuit density, either of which improves the yield. (Obviously, the designer might choose instead to augment the functionality, performance or capacity of the design.)
  • Some devices contain large numbers of identical parts – memory cells, sensor elements, etc. In these devices, redundant elements are typically included to “repair” defects. Good designers, taking advantage of the increased connectivity and proximity in 3D devices, can create extremely effective repair schemes. This dramatically increases the yield of finished parts.


Because there is no “standard” stacking method, yield issues must be evaluated separately for each of today’s many proprietary methods. In general, it can be stated that 3D wafer stacking reduces die size, extends the useful life of mature geometries and can often use fewer mask steps per wafer. On the other hand, wafer stacking introduces new risk factors such as misalignment, bond contamination and peeling. The single greatest yield benefit available in 3D is in the design phase: Good designs will maximize process separation and optimization, add robustness and employ redundancy/ repair schemes. As stacking processes mature, the greatest yields will be realized by those methods that allow chip designers the greatest flexibility.

About the Author

Robert Patti

Robert Patti is founder and CTO of Tezzaron Semiconductor (memory components, wafer-level stacking). Prev-iously he was founder, president and CEO of ASIC Designs. He participated in over 100 IC designs and many end-user products; holds 14 U.S. patents; serves on several boards; and is vice chairman of JEDEC’s Future Memories task group.


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