With distinctly different technology
demands, wafer fabs and assembly and
packaging service companies generally
meet only at the bond pad. A clear delineator
between “front end” (wafer fabs)
and “back end” (packaging) exists, and in
many cases are oceans apart.
With distinctly different technology demands, wafer fabs and assembly and packaging
service companies generally meet only at the bond pad. A clear delineator between
“front end” (wafer fabs) and “back end” (packaging)
exists, and in many cases are oceans apart. As silicon stacking moves into the
mainstream, both are poised to enter into new process areas. But will 3D stacking
processes evolve in totally different directions, or is the boundary between
“front end” and “back end” blurring? Can both sides
learn from each other, and leverage each other’s expertise, forming a
new connection? The opportunity to build a bridge exists – and we call
it a through-silicon via (TSV).
3D integration is a fast-growing field that can encompass many different types
of processes. In this paper, the term refers to any process flow that contains
more than one device layer. For example, a second layer of devices can be formed
on a wafer by adding a layer of polysilicon or amorphous silicon, which subsequently
is processed to form load transistors. Alternatively, two separate wafers can
be bonded together using a variety of bond layer materials. Individual die can
be wire-bonded or bump-bonded to other die to create a system in a package (SiP).
Finally, connection can occur at the package level with a package-on-package
(PoP) solution. The 3D integration method chosen will be determined by the needs
of the end product.
One of the most rapidly growing market segments for 3D integration via SiP
is the cell phone market. The consumer wants new products with increased
functionality, such as higher-resolution cameras, music streaming capability
or email. The product life cycles in a consumer-driven market are also typically
very short – in some cases less than a year. This places huge demands
on the device-development cycle – the packaged chips must be small, thin
and low cost, and hit a rapidly evolving market window. The 3D integration method
chosen must support these constraints, i.e., be inexpensive and fast to implement.
At the other end of the 3D spectrum lies the high-performance processor. According
to the International Technology Roadmap for Semiconductors (ITRS), microprocessors
drive the entire industry forward, operating at the extreme end of the performance/power
envelope. There are challenges, though. While device scaling continues to drive
the clock frequency forward, the DRAM speed is not increasing at the same rate,
as shown in Figure 1. This rapidly increasing performance gap can be addressed
by utilizing caches, but if the CPU cannot find the data item it needs, resulting
in a cache miss, the data must be fetched from main memory. It can take several
clock cycles for the CPU to resume, and the resulting latency has actually gotten
worse over time. The solution lies in getting the memory closer to the processor
– and by shortening the wires, an additional power savings can potentially
be realized. The 3D integration method chosen here must be able to deliver adequate
interconnect density between the die.
Through-Silicon Via Evolution
At first glance, the market drivers and process flows for a mobile phone chip
set and those of a high-end microprocessor don’t appear to have anything
in common, other than the raw silicon starting material. For a mobile phone,
existing die are stacked together into an SiP with a relatively low density
of vertical interconnections between the chips. The primary benefit is again
a low-cost solution for minimizing the total chip area, with integration typically
done at assembly and packaging services companies. To achieve the performance
gains and power reduction benefits of 3D, a microprocessor would need a much
higher level of vertical interconnect density. If increasing vertical interconnect
density is the direction of the future, we need to define a roadmap to get there.
We need to understand how 3D integration will evolve from the stacked die of
today, to the high-density devices of the future.
A proposed evolutionary pathway is shown in Figure 2. This evolution will occur
in both the assembly and packaging services companies and the wafer fabs. The
vertical interconnect density will increase as we move from phase one to phase
four. A key component of this phased evolution is that processes will become
more “fab-like” in the assembly houses, and more “assembly-like”
in the wafer fabs. One process module that will be common in both assembly service
companies and wafer fabs is the TSV module.
On the assembly side, processes are evolving rapidly from the Phase 1 SiP and
PoP approaches in high volume today, to Phase 2 wafer scale packaging technologies.
Die-to-die connections using TSVs already have been demonstrated by Samsung.
By eliminating the vertical gaps required for stacked wire-bonded chips, the
resulting die stack was reported to be 30 percent thinner. The vias are relatively
large and fewer in number; thus, technologies such as laser drilling can be
used cost-effectively. As the density of required connections increases, however,
there will be a cost crossover point where batch processes such as reactive
ion etching (RIE) will be more cost-effective. In addition, the laser process
may not be scalable to smaller diameters, and the area penalty for each via
also must be considered. The ability to scale the process, with a push toward
more advanced “fab-like” processes, must be carefully weighed with
respect to the cost.
Phase 3 will allow a much higher interconnect density between the two tiers
of silicon by utilizing a face-to-face contact. The final metal layer of the
wafers to be bonded must be designed for the interconnect structure, typically
using copper pads with pitches in the range of 10-20 µm. With the oxide
slightly recessed from the pad, and applied heat and pressure, a bonded interface
is formed between the two wafers. A significant advantage to this process flow
is that a fairly high density of vertical interconnects (~105 per cm2) can be
achieved without an active area penalty. For a die-to-wafer flow, external contact
then can be made to bond pads at the periphery of the bottom die. If two wafers
were bonded face-to-face, external contacts must be made using through-silicon
vias, as shown in Figure 3.
Another distinct advantage of a face-to-face bonding process is that the backside
of the top wafer can be thinned without the process complication of handle wafers.
As shown in the figure, the silicon has been completely removed, to stop on
the base oxide of the top wafer, which was assumed to use silicon-on-insulator
(SOI) starting material. Using SOI simplifies the thinning process by providing
a natural etch stop. If the top wafer uses bulk silicon starting material, control
of the thinning is critical. If there is significant nonuniformity in residual
silicon thickness, additional overetch must be built into the TSV etch process.
Excessive overetch could damage the underlying metal pads.
final phase has a very high level of interconnect density, with 3D designed
in as part of the overall process flow. To keep the active area penalty to a
minimum, vias must be strategically placed where they are needed, and the via
diameter must be minimized. Several processes affect the ability to shrink the
TSV diameter. The ability to fill the via with metal depends on the via aspect
ratio, which is the ratio of the via depth to via diameter. Copper seed layer
coverage in the via is critical for successful electroplated fill. As the aspect
ratio increases, physical vapor deposition (PVD) seed layer coverage will start
to degrade at the bottom sidewalls of the via, resulting in copper voids during
the plating process. Tungsten chemical vapor deposition (CVD) metal deposition
can be used as an alternate conductor, achieving fill at higher aspect ratios.
The target depth of the via can be improved if an aggressive thinning process
is used. (Thin is definitely in, for both assembly and wafer fab process flows.)
The final limit to via diameter is the ability to align one wafer or die to
another. There must be adequate overlap to ensure successful electrical contact.
If the wafers are perfectly aligned in the center, one degree of thermal mismatch
between two wafers during the bonding process can cause a 0.5 µm misalignment
at the edge, again limiting the ability to aggressively shrink the via diameter.
TSVs can thus be broadly categorized into two different types, according to
the density of vertical interconnect that is needed, as illustrated in Table
1. Target product applications also are shown in the table. As the TSV processes
mature and are scaled, an opportunity exists for cooperation and information
sharing between front and back end. This cooperation is starting already, with
the ITRS roadmap committees in Interconnect and Assembly and Packaging. Both
teams are working together to define a new roadmap for TSVs.
Technology demands are driving the development of new 3D processes, with potential
benefits in form factor reduction and improved performance. 3D processes are
evolving both in wafer fabs and packaging companies, with each developing new
TSV processes. An evolutionary pathway has been proposed that will allow a smooth
transition to higher vertical interconnect densities, as the critical processes
mature to enable scaling.
- H. M. Tong, “SiP Technology Overview,” presented at the 2007
FSA System-In-Package (SiP) Technical Conference, Jan. 23-24, 2007.
- J. Walker, “SiP Application and Business Trends,” presented
at the 2007 FSA System-In-Package (SiP) Technical Conference, Jan. 23-24,
- International Technology Roadmap for Semiconductors (2005 edition)
- N. Mahapatra and B. Venkatrao, “The Processor-Memory Bottleneck:
Problems and Solutions,” see http://www.acm.org/crossroads/xrds5-3/pmgap.html.
- J. McCalpin, "STREAM: Sustainable Memory Bandwidth in High Performance
Computers," a continually updated technical report (1991-2007), see http://www.cs.virginia.edu/stream/.
- N. Moskowitz, “3D Wafer Level Interconnect: The Next Wave of Electronics
Packaging," presented at 3D Architectures for Semiconductor Packaging
Conference, Oct. 31-Nov. 2, 2006, see http://www.prismark.com/.
- “SAMSUNG Develops 3D Memory Package that Greatly Improves Performance
Using Less Space,” Press Release April 13, 2006, see http://www.samsung.com.
About the Author
Susan Vitkavage, Ph.D., manages SEMATECH’s 3D Interconnect Project, which
focuses on prioritizing infrastructure needs, defining a roadmap for 3D and
developing a cost model for 3D integration. Prior to joining SEMATECH, Dr. Vitkavage
spent 15 years as a senior manager for Bell Laboratories, where her group was
responsible for development and manufacturing transfer of advanced interconnect
processes to the company’s worldwide fab locations. She may be reached