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The Impact of DRAM Design Innovation on Manufacturing Profitability
(11/6/2010) Future Fab Intl. Issue 35
By Kenneth Flamm, University of Texas at Austin
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One recurring theme in the ITRS process is the desire to identify when forecasted technological developments are likely to occur, and to understand what the consequences of the timing of those developments are likely to be. Most of the focus in the ITRS is on the technology itself, but clearly there are important economic consequences of choices that are made in accelerating or delaying the delivery of new technologies.

This paper summarizes certain results from a more detailed working paper. See Kenneth Flamm, "How Does The Timing Of Technical Innovation Affect Semiconductor Manufacturing Profitability?", University of Texas at Austin, September 2010.

The International Technology Roadmap for Semiconductors (ITRS) is a unique, private-sector-led, global initiative formed to coordinate, and thus accelerate, the introduction of new design and manufacturing technology into the semiconductor industry.[1] The ITRS includes a roadmap for DRAM design and manufacturing technology that is updated annually using information provided by all major semiconductor producer company participants, and is often used as a framework for discussion of industrial trends in business and academic circles.

One recurring theme in the ITRS process is the desire to identify when forecasted technological developments are likely to occur, and to understand the likely consequences of the timing of those developments. Most of the focus in the ITRS is on the technology itself, but there are important economic consequences of choices made in accelerating or delaying the delivery of new technologies. These economic consequences are understood at some intuitive level, but rarely analyzed or spelled out with the more rigorous level of discussion devoted to purely technical issues.

This paper shows how simple methods of economic analysis can be coupled with equally simple, widely used models of semiconductor fabrication costs, to develop useful answers to interesting questions about the economic implications of changes in the adoption times for specific innovations that affect semiconductor manufacturing. The integration of economic methods with cost and yield models is illustrated with a detailed case study of the economic benefits derived from a specific historical technological innovation – the recent shift in DRAM designs from an 8F2 cell size to a 6F2 cell size (and the ITRS forecasts an upcoming shift from a 6F2 to a 4F2 memory cell size). I show how an estimate of the economic benefit from accelerating (or retarding) these transitions by one year can be derived by applying standard economic analysis to the industry frameworks used to predict manufacturing costs and yields.

Historical Context

Improved designs for DRAMs that reduce the physical footprint of a storage cell in a memory array have historically enabled significant increases in DRAM density and reductions in DRAM die size, and thus reduced production cost. Figure 1 is based on a Micron Technology public presentation comparing the ITRS 2006 roadmap DRAM cell size with actual adoption of smaller cell designs by specific DRAM producers, and demonstrates how the ITRS methodology has become an accepted benchmark within the DRAM industry for analyzing the implications of adopting specific technological innovations.

As part of the ITRS planning and forecasting exercise, the global semiconductor technology community estimates die sizes for current and future leading-edge products in production, including DRAM. The methodology used for estimating die size splits the DRAM's total area into two parts: the memory cell array, and the peripheral areas of the DRAM. The ITRS model estimates die memory cell area per bit by multiplying the critical feature size squared, F2 (F is the DRAM "half pitch,” the minimum feature size that can be produced using a given generation of manufacturing technology, and also an index of the generation of manufacturing process technology – the "technology node" – being used in production), the area of the smallest feature that can be created on the chip,[2] by a "cell area factor.” The cell area factor has declined dramatically over the last 20 years with advances in DRAM design, from a range of 16 to 22 times F-squared in 1995, to 6 to 8 times F-squared in 2004 (Figure 2). ITRS roadmaps and roadmap updates through the current 2009 version show leading-edge DRAM cell area factor dropping from 8F2 to 6F2 in 2006, then continuing at 6F2 through 2010.[3]

The remainder of the DRAM die area, per bit, which holds peripheral circuitry, was modeled by the ITRS as another constant factor times F2.[4] It is straightforward to determine that the ITRS calculated peripheral circuitry per bit as 4.70 times F-squared from 2005 to 2009. This factor did not change when advances in DRAM design led to a 2006 decline in the cell area per bit from 8F2 to 6F2. This led to a decline in cell efficiency from 63 percent to 56 percent in the ITRS.[5]

Figure 1 also supports the point that early adoption of the 6F2 cell design gave Micron a real production cost benefit when manufacturing using any given generation of wafer processing technology, by allowing it to squeeze more chips on a wafer. Since wafer-level fabrication costs for DRAMs are typically viewed as approximately constant for a given technology node, shrinking die size directly translates into more chips produced per wafer, and thus, lower cost per chip. Micron moved this design innovation into volume production of its DRAMs around 2004. As Figure 1 suggests, the next producer to do so, Samsung, did not do so until 2006. In response to these developments, the ITRS roadmap for 2007 pulled in the adoption date for the 6F2 cell two years, to 2006.[6]

Adopting next-generation process technology is an equally important route to downsizing a DRAM die, and Samsung has a well-earned reputation in the industry for aggressive investments, and time schedules, in adopting new process technology. Thus, its die sizes for DRAMs were competitive, despite its relative lag in moving to the 6F2 cell.

Nonetheless, it is instructive to consi-der what the economic impact of adopting the 6F2 cell design a year earlier, in 2005, would have been on Samsung's bottom line. Because there is a substantial amount of public information available on Samsung's DRAM products and introduction dates, this is a useful case study to illustrate how economic methods can be used to assess the implications of acceleration or delay in introducing a significant technological innovation.[7]


In presenting this case study, I have assumed that market prices for DRAMs in 2005 would not have been affected by Samsung's adoption of the 6F2 cell in 2005. I have elsewhere undertaken a more sophisticated sensitivity analysis that allows DRAM price to decline as Samsung output increases.[8] Existing econometric studies suggest that DRAM demand is quite price elastic;[9] that is, sensitive to price, and as a result, allowing price to decline with increases in Samsung output has only a small impact on the estimated economic value of earlier adoption of this innovation by Samsung.

My economic model of DRAM cost adopts standard methods employed in the DRAM industry to analyze technical and economic factors influencing DRAM production and investment decisions.[10] I first describe my methodology, then briefly discuss empirical parameters used in this analysis. I estimate the reduction in size of a DRAM die were the DRAM memory cell array designed using a 6F2 cell in lieu of an 8F2 cell size, using parameters corresponding to a product actually produced in a "leading edge" Samsung fab in 2005. The peripheral areas on the DRAM die, per bit, are also estimated using actual values observed for a Samsung DRAM die produced using actual process technology. Samsung reported it was manufacturing 512 Mb DDR2 DRAM parts in volume using 90 nm process technology in 2005.[11]

Calculation of DRAM Die Size After Adopting the 6F2 Cell

To estimate the reduction in DRAM die sizes that would have resulted from shrinking the memory cell array on DRAM dice, I employed the same methods of analyzing DRAM die size utilized in the ITRS.[12] As employed, the methodology is inherently conservative in projecting die size reductions, as the peripheral areas of the chip would likely also decrease somewhat in size as the cell array size decreased.[13]

Publicly available Samsung investor presentations state that Samsung began making 512 Mb DRAMs in volume using 90 nm technology in 2005. I base my calculations on nonconfidential data derived from a "tear-down" of an actual Samsung 512 Mb DRAM die produced at the 90 nm technology node (Table 1). Note that the cell area factor in this "8F2" design is actually somewhat larger than the idealized 8, clocking in at 8.64. I will assume that the 25 percent reduction in cell area factor in going from an idealized 8F2 cell size to an idealized 6F2 design would scale down the real-world cell area factor by the same proportion, to 6.48.

If e is the memory cell array efficiency (the share of functional memory cell area in total die size) in the original die design, and peripheral area per bit is unchanged when the memory cell area is shrunk by 25 percent (i.e., going from an 8F2 to a 6F2 cell design), then it is easy to show algebraically that the downsized die area is (1 - .25 e) times the original die area. As the original die cell efficiency shown in Table 1 was 55.3 percent, a 25 percent reduction in memory cell size translates into a 13.8 percent reduction in die size.

Economic Value of Smaller Die Sizes Enabled by the 6F2 Memory Cell

Given this die size decrease, I can now undertake an analysis of the economic benefit to Samsung of earlier adoption of the 6F2 cell. Now, let us consider the economic calculus faced by Samsung had it considered investing in acceleration of development of 6F2 DRAM memory cell technology for use in mass production in 2005.

One effect of smaller die sizes is to increase yield rates of "good” chips per wafer. For any given number of "killer” defects on a wafer, producing with smaller dice means a smaller fraction of the chips produced from that wafer must be discarded as nonfunctional. A widely used approximation for modeling the relation between die size and chip fabrication yield in the semiconductor industry is the Poisson yield model.[14] Given a fixed number of critical defects per 300 mm wafer, the effect of decreasing die size from A1 to A2 is to increase the yield rate for good chips at the smaller size die, y2, to a level equal to y1(A2/A1), where y1 is the yield rate for the original die area A1. I used this relation to model increases in yields due to smaller die sizes with reduced dimensions in memory cell arrays. I have conservatively assumed that the yield of good chips on a wafer at the end of the "front end" wafer fabrication process ("probe yield"), but before required "back end" assembly and test, would be 95 percent for a 512Mb DRAM manufactured in 2005.

If the radius of a silicon wafer is r, and the area of a die is A, then the number of die that can be fit on the wafer, d, is approximated by

The second term in this formula adjusts down the die count to reflect that rectangular dice cannot utilize some wafer area at the edge of a round wafer.[15]

Let us call the historical scenario utilizing the 8F2 (actually 8.64F2) cell the production "baseline” for an exemplary leading-edge Samsung DRAM wafer fab. Given estimates of actual prices for DRAM products in 2005,[16] we can apply a simple model of the DRAM fabrication process based on estimated die sizes, and assumptions about yields, to produce an estimate of additional revenues per 300 mm wafer produced at this fab in 2005 as the result of adopting a 25 percent smaller memory cell size.

Expressed mathematically, the revenue model is

Rt fab revenues from sales of DRAMs fabricated in year t,
dt die per wafer in year t, dependent on product and technology node,
yft good die yield rate at probe test at end of front end fabrication,
yat good chip yield rate for assembly and test, back end of production process,
Pt price per chip of yielded good chips sold in market,
N wafer capacity of fab, annual wafer starts (also known as "wafer-ins”)
Ut, utilization rate, actual annual starts as fraction of capacity.

Similarly, based on assumptions about the variable wafer fabrication costs for a wafer containing DRAMs at the 90 nm technology node, and the variable costs of assembling and testing the good, yielded dice produced on this wafer, we can estimate the variable costs in 2005 associated with producing the wafers that yielded the previously described DRAM revenues. Expressed mathematically, the cost model for variable manufacturing costs is

Ct variable costs
cft front end wafer variable fabrication cost per wafer fabricated,
dt defined as in (1) above,
yft defined as in (1) above,
cat back end assembly and test cost per good front end die,[17]
N defined as in (1) above,
Ut defined as in (1) above.

The expressions in both (1) and (2) show that economic calculations of fab revenues, Rt, and variable costs, Ct, are proportional to annual wafer starts, N Ut. We are interested in the impact of adopting a smaller DRAM cell size, and die size, in production. Using the symbol Δ to denote a change in a variable relative to the larger cell size baseline, our expression for the economic impact of use of the downsized die design, the incremental change in profit per wafer processed, is

Dividing by annual wafers processed, N Ut, we have

This expression makes it clear that the change in yielded chips per wafer (dt yft) in the front end fabrication process primarily drives the economic impact. Adopting the improved cell design would augment revenues by increasing the number of fabricated chips that can be sold at the market price after assembly and test; however, with more chips fabricated, there are more chips to be assembled and tested, increasing one element of cost and somewhat offsetting the additional revenues.

When considering making an earlier investment in die redesign, to reap the economic benefits of the smaller die size in 2005, a producer would also want to weigh the cost of accelerating its DRAM design R&D. Samsung ultimately made the investment needed to develop 6F2 cell technology, introducing this design feature into mass production in 2006. A complete calculation of the economic impact of accelerating the introduction of the smaller memory cell by a year would also account for moving forward in time the costs of perfecting the 6F2 cell. Time really is money, and Samsung, when it was considering this investment, would logically want to take the difference between the present value of the R&D costs if undertaken earlier, less the present value of those R&D investment costs if undertaken later, as an incremental cost partially offsetting the economic benefits described by (3).

Unfortunately, we do not have access to public, nonproprietary data on what development of its 6F2 DRAM cell cost Samsung, when it started and when it was ready for use in volume production. So, the costs of acceleration of this development effort cannot be netted out from my calculation of the economic benefits.

Figure 3 reports my calculation of the economic benefits to Samsung of advancing its use of the 6F2 cell by a year, to 2005, rather than in 2006. The 13.8 percent smaller die size would translate into an incremental profit of $1,030 per processed wafer in 2005, amounting to 16.5 percent of actual revenues received from processing those wafers in 2005 without accelerating the adoption of the innovation. This is a large benefit, and illustrates how critical small changes in die size – or yields – can be to competitive economic advantage in the semiconductor business.

This conclusion is not dependent on the details of the production scenario. If, for example, we were to suppose instead that the Samsung fab were to produce 1 Gb, rather than 512 Mb DRAMs throughout 2005, the economic benefit would increase to 18 percent of baseline 2005 revenues. This is because the same numbers of total bits on the wafer would be divided into a smaller number of larger chips in order to be sold, with lower probe yields that would benefit relatively more from downsizing the die, and because the incremental costs associated with assembling and testing the larger number of downsized chips would be smaller. Similarly, a much lower initial probe yield rate of .85 would raise the economic benefit to 18 percent of 2005 revenues.

If we discount that 2005 incremental profit back to 2004, using an estimate of Samsung's weighted average cost of capital as the discount rate, this value would be 886 year-2004 dollars per wafer pro-cessed in 2005. I used a 16.24 percent discount rate.[18] Expressing the 2005 economic benefit in 2004 dollars also reminds us we need to consider the changes to the stream of R&D investments over time that later create benefits in production, when evaluating the entire picture of costs and benefits flowing from accelerating innovation.

Calculations would be somewhat more complicated if the benefits extended over more than a single year. We would then need to forecast how wafer starts varied from year to year, if capacity or utilization were not constant, and calculate present value over a series of years. Fortunately, dealing with these complications is reasonably straightforward.[8]


I used the shift from an 8F2 to a 6F2 memory cell in DRAMs to illustrate how a simple economic framework can be used to estimate the benefit from earlier adoption of a technological innovation in semiconductor manufacturing. The parameters used in my framework can be derived from tables found in the ITRS roadmap, and thus these methods can be used to answer questions about the timing of technological changes – how much is it worth to move up a shift by one year, or how costly would it be to wait an additional year? What are the likely economic consequences of all producers making this shift a year earlier or later?

Because this case study dealt with what was primarily a semiconductor design innovation, it was reasonable to take the existence of wafer fabs, and the technology and equipment within them, as appoximately fixed, a given. But the same framework can also be used to analyze economic costs and benefits associated with accelerating or retarding innovations embedded in semiconductor production facilities and equipment. Rather than simply looking at how variable production costs change, we would also need to consider what kinds of changes in fixed investments in capital equipment would be required. Expressions analogous to (3) and (4) can be redefined to include capital investment costs. These methods could be used to analyze the economics of a perennial theme of hot debate in the ITRS over the years: Is the most desirable lag between new technology nodes two years, 2 1/2 years or three years?


  1. See K. Flamm, "Economic Impacts of International R&D Coordination: SEMA-TECH and the International Technology Roadmap,” in S. Nagaoka et al. Eds., 21st Century Innovation Systems for Japan and the United States: Lessons from a Decade of Change, (Washington: National Academies Press), 2009.
  2. F2 is the area of an F by F square.
  3. The 2009 ITRS roadmap forecasts that cell area factor in DRAM will drop to 4F2 in 2011.
  4. This is easily verified by noting the ratio of the cell array area to the total DRAM die size ("area efficiency”) is constant during 2006-2009 in ITRS roadmaps after 2006.
  5. Since cell area efficiency = cell area factor / (cell area factor + peripheral area factor). Prior to 2007, cell area efficiency was 8 / (4.7 + 8) = .63; from 2007 on, cell area efficiency was 6 / (4.7 + 6) = .56.
  6. See Alan Allan, "2007 ITRS: Some Overview Highlights,” available at http://mast-tech.com.tw/itrs_jan08.pdf, p. 11.
  7. Samsung and its affiliates have neither supported nor contributed to this analysis, and have neither approved nor endorsed it. I would like to thank Advanced Micro Devices, Inc., for supporting this research by assisting me in finding some of the public, nonproprietary information used, and permitting me to use public information uncovered with their assistance.
  8. See K. Flamm, "How Does The Timing Of Technical Innovation Affect Semiconductor Manufacturing Profitability?”, University of Texas at Austin, 9/10.
  9. For evidence that the price elasticity of demand is between -1.5 and -2, see the sources cited in Leachman et al. "Inte-gration of speed economics into decision-making for manufacturing management,” International Journal of Produc-tion Economics, vol. 107, 2007, p. 44.
  10. These methods for calculating chip manufacturing costs are summarized in Rabaey et al. Digital Integrated Circuits: A Design Perspective, 2nd Edition (Prentice Hall), 2002, pp. 21-23; Hen-nessy et al. Computer Architecture: A Quantitative Approach, 4th Edition (Elsevier Morgan Kaufman), 2007, pp. 21-25.
  11. See "Samsung Electronics,” Investor Relations Presentation, 11/04, http://www.samsung.com/sec/aboutsamsung/file/ir/irevent/conference/ir_japanese_investor.pdf; T.S. Jung, "Memory Technology and Solutions Roadmap,” Samsung Analyst Day Presentation, 11/05, http://www.samsung.com/us/aboutsamsung/ir/ireventpresentations/analystday/downloads/analyst_200 51104_0800.pdf; T.S. Jung, "Memory Technology and Solutions Roadmap,” presentation at Samsung Tech Forum, 11/06, available at: http://www.sec.co.kr/images/corp/ir/irevent/techforum_01.pdf; Samsung presentation at Prudential Investors Forum, 5/08, available at http://www.samsung.com/sec/aboutsamsung/file/ir/irevent/conference/20080522_prudential.pdf.
  12. See 2009 ITRS Executive Summary, pp. 73-75, Tables 2009 ORTC-2A, 2009 ORTC-2B, available at http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_ExecSum.pdf, http://www.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009Tables_FINAL_ORTC_v14.xls; 2008 ITRS Update, Tables 2008 ORTC-1CD, 2008 ORTC-1EF, available at http://www.itrs.net/Links/2008ITRS/Update/2008Tables_FOCUS_A.xls.
  13. This in part is because what have been classified as "peripheral” areas of the chip typically contain some redundant memory cells, which are utilized to repair the chip and make it functional in recovering from some manufacturing defects.
  14. See, e.g., H. Nakatsuka, "Derivation and Implication of a Novel DRAM Bit Cost Model,” IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 2, 5/02. As noted in "Yield," Chap. 36 in S. Franssila, Introduction to Microfabrication (Wiley), 2004, p. 36, the Poisson model "holds fairly well for small chips and/or low defect densities.”
  15. There are many approximation formulae for gross dice per wafer in use. For empirical evidence on the accuracy of this particular one, see D.K. de Vries, "Investigation of Gross Die Per Wafer Formulas,” IEEE Transactions on Semiconductor Manufacturing, vol. 18, no. 1, 11/05.
  16. My price estimate for 2005 is based on analyst estimates of historical blended DRAM Average Selling Price for a 1 Gb chip equivalent, as reported in S.D. Woo et al. "Top 5 predictions for 2010-12,” Global DRAM/NAND, Bank of America Merrill Lynch, 2/23/10, Tables 7, 10. Price for a 512 Mb chip is estimated as .5 times the 1 Gb price reported in this source.
  17. Based on 2009 estimates averaged over all DRAMs produced within different technology nodes, I conservatively assumed total back-end assembly and test costs of $0.35 per die. See Wang, "DRAM Market Outlook,” Morgan Stanley Research presentation, SEMICON Taiwan 2009, 9/09, p. 24.
  18. Estimated weighted average cost of capital (WACC) for the U.S. semiconductor industry in 2004. See "Cost of Capital by Industry Sector,” spreadsheet available at http://www.stern.nyu.edu/~adamodar/pc/archives/wacc04.xls.

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