Home
About Future-Fab
Download New Issue
Contact Us
Volume Archives
Editorial Panel

FUTURE FAB ARCHIVES


Interconnect Test for Wide-IO Memory-on-Logic Stacks
(7/5/2012) Future Fab Intl. Issue 42
By E.J. Marinissen, imec
S. Deutsch, Cadence Design Systems
B. Keller, Cadence Design Systems
V. Chickermane, Cadence Design Systems
S. Mukherjee, Cadence Design Systems
N. Sood, Cadence Design Systems
Print Article Print this paper
Send As Email Send as email

Why 3D-SICs based on fine-pitch micro-bumps and TSVs promise heterogeneous integration with dense high- performance low-power inter-die connections.

Interconnect Test for Wide-IO Memory-on-Logic Stacks

E.J. Marinissen,¹ S. Deutsch,² B. Keller,² V. Chickermane,² S. Mukherjee,² N. Sood²

¹imec ²Cadence Design Systems

Three-dimensional die stacks with inter-die connections based on fine-pitch micro-bumps and through-silicon vias offer the promise of heterogeneous integration with dense high-performance low-power inter-die connections. These 3D stacked ICs (3D-SICs) come in a variety of form factors. The interposer-based 3D-SIC has multiple active dies placed side-by-side on top of and interconnected through a silicon interposer base. Such products are attractive for high-performance computation and communication applications, as they offer high-bandwidth interconnect between the various active dies and good cooling opportunities. Another type is the tower of stacked active dies. Offering a small footprint, this type is particularly attractive for handheld and portable consumer electronics. For the future, we can also expect hybrid combinations of the two form factors, i.e., multiple towers of active dies stacked onto a silicon interposer base.

Like all microelectronics products, 3D-SICs need to be tested for manufacturing defects. Especially for post-bond testing, this requires a test access architecture that operates in a concerted way across the entire die stack. Test access (through a probe card for unpackaged devices or a test socket for packaged products) is through the external I/Os only, which are typically located in the bottom die of the stack. This implies that if we want to test a middle or top die in the stack, the dies below it need to cooperate in order to propagate test stimuli up to and test responses down from the die-under-test. Testing inter-die interconnects requires an even more orchestrated cooperation between the multiple dies in the stack.

3D DfT Architecture for Logic-on-Logic Stacks

In the recent past, we have defined,[1-3] automated,[4] and used[5] a 3D design-for-test (DfT) architecture for logic-on-logic stacks. The main component of that architecture is a die-level DfT wrapper that provides test control and test access functionality at each die in the stack. The 3D die wrapper is an extended version of the IEEE Std 1500 wrapper, originally developed for embedded IP cores. The 3D wrapper has a primary test interface at the die’s bottom side, and one (or k, in case of k towers) compatible secondary test interface(s) at the die’s top side, such that the primary test interface of die x+1 can be stacked on top of the secondary test interface of die x. Each interface consists of test control signals, a serial (one-bit) test access mechanism (TAM), and an optional scalable (n-bit, with n user-defined) parallel TAM. The serial TAM is used to transport test mode instructions and low-bandwidth test data. The parallel TAM is meant for high-bandwidth volume-production test data. A schematic view of our 3D DfT architecture is depicted in Figure 1. The figure shows a single-tower vertical die stack consisting of N dies; for layout reasons, the stack in the figure is rotated 90° clockwise, such that the bottom and top dies are left and right, respectively. The functional die designs are represented by gray boxes, of which only the internal scan chains are shown. The die-level wrapper is the rose circuitry around the functional die design; because we focus here on the wrapper design, it is shown enlarged in Figure 1, but in reality it is negligibly small compared to the functional die-internal circuitry.

Figure 1. Schematic View of the Logic-on-Logic 3D DfT Architecture

Our 3D DfT architecture leverages existing intra-die DfT features such as internal scan, test data compression (TDC), built-in self-test (BIST), and core-based wrappers and TAMs, as well as boundary scan at the 3D-SIC’s PCB interface, and requires no additional product-level pins. The architecture serves the test needs for die maker(s), stack maker and stack user alike, by providing support for (1) pre-bond die testing; (2) mid-bond testing for partial stacks; (3) post-bond testing for complete stacks; (4) board-level interconnect testing; and (5) (low-bandwidth) in-field test and debug. The architecture supports a modular test approach, in which dies and their embedded cores, as well as inter-die interconnects, can be tested separately. The architecture provides maximum freedom with respect to inclusion or exclusion of certain tests at a particular stage of the test flow, and allows for flexible (re-)scheduling of those tests in order to optimize the test flow and minimize the associated test costs. We have shown that the area costs for medium and large industrial SOCs are negligible.[2-5] The 3D DfT architecture is currently considered for standardization by the IEEE P1838 Working Group.[6]

JEDEC Wide-IO Mobile DRAMs

Given the ever-growing hunger for more memory bandwidth and the need to reduce memory power in many appli-cations, it is no surprise that memory-on-logic stacks are among the first stacked-die applications that are appearing on the market.[7,8] JEDEC, an industry association that develops and maintains open standards for the microelectronics industry, has recently released its first standard for stackable Wide-IO DRAMs (JESD-229).[9] This standard widens the conventional 32-bit DRAM interface to 512 bits. The main benefit of wide-IO DRAM over its predecessors (such as LPDDR2 DRAM) is that it offers more bandwidth at lower power. Being the first interface standard for 3D die stacks and offering a compelling bandwidth/power benefit, this standard is expected to gain quite some traction in the marketplace.

The standard defines the functional and mechanical aspects of the wide-IO logic-memory interface. The functional aspects include the electrical specification, usage protocols and ball-out. JEDEC’s wide-IO logic-memory interface defines four independent memory channels (a, b, c and d) of 128 bidirectional DQ data bits each, totaling 512 data bits over all four channels. The maximum data rate is 266 Mbps (single data rate), which offers a total logic-memory bandwidth of 512 x 0.266/8 = 17 GBs. Next to the data bits, each channel includes independent control and clock, and shared power and ground.

Figure 2 (a) JEDEC wide-IO rank; (b) an example of 3D-SIC containing a logic die and four stacked wide-IO ranks

The mechanical aspects of the standard include the pad locations, dimensions and tolerances. The interface consists of 300 (micro-bump) pads per channel, making 1,200 connections for all four channels. The pad locations are symmetrical between the four channels. Each channel consists of six rows by 50 columns of (micro-bump) pads at a pitch of 40 µm in the short axis and 50 µm in the long axis.

JEDEC’s wide-IO interface allows for stacking of up to four DRAM dies ("ranks" in JEDEC jargon) on top of each other. Each rank has four memory blocks, as depicted in Figure 2(a); the logic-memory micro-bump interface is located symmetrically in the center of the die. A complete stack with a bottom logic die and four stacked DRAM ranks is shown in Figure 2(b). Such a four-rank stack consists of 16 memory blocks, of which only four blocks (i.e., one per channel) can be accessed at a time. The JEDEC wide-IO DRAM allows for a variety of stack configurations; the industry has reported on prototype chips where a logic die and a stack of four wide-IO DRAMs are stacked side by side on a passive silicon interposer, as well as on a single-tower 3D-SIC consisting of two logic dies and a single wide-IO DRAM rank.[8]

Figure 3. JEDEC Wide-IO DRAM Boundary Scan Implementation per Memory Block

3D DfT Architecture Extension Supporting Wide-IO DRAM Boundary Scan

Our original 3D DfT architecture focused on logic-on-logic stacks, motiv-ated by the fact that DfT can be freely defined and inserted in CMOS logic designs. Due to technology, design and performance constraints, free definition and insertion of DfT in DRAMs is typically not possible. Fortunately, unlike many previous DRAMs, JEDEC’s wide-IO standard contains boundary scan features to facilitate interconnect testing.[9] This boundary scan implementation, which by the way is not compliant with the well-known IEEE 1149.1 boundary scan standard, is depicted in Figure 3. Next to a functional (transparent non-test) mode, it supports serial scan access and "parallel in" (= capture in the DRAM) and "parallel out" (= capture in the logic die) test modes.

We have extended our logic-on-logic 3D DfT architecture with support for post-bond testing of the interconnects between the logic stack and wide-IO DRAMs, which can be stacked on top or next to the logic stack by means of a silicon interposer. The extension includes the generation in the top logic die of DRAM test control signals, and the inclusion of the DRAM boundary scan registers in the serial and parallel TAMs of the 3D test access architecture. Figure 4 highlights the DfT extensions to the original architecture in green. They include 13 new bits in the wrapper instruction register (WIR) for enabling the DRAM boundary scan, selecting the DRAM channel(s), and selecting the DRAM rank(s). This implementation allows us to test interconnects between the top logic die and any combination of DRAM blocks.

Figure 4. 3D DfT Wrapper Extension for Wide-IO DRAM Control

We have set up flows for automatic insertion of the required 3D DfT in a given design with Cadence’s Encounter RTL Compiler, and for automatic generation of interconnect test patterns with Cadence’s Encounter Test. Our interconnect ATPG approach covers static stuck-at faults, slow-to-rise and slow-to-fall faults, and shorted nets. For realistic test cases, the ATPG run time is only a handful of minutes, while yielding high fault coverage (>99.9 percent of all test objectives) with only a few dozen test patterns.

The tool flow was put to first use on an industrial design consisting of a silicon interposer base, a logic SOC die and a wide-IO DRAM stack. The DfT was automatically inserted into the logic die using the tool flow mentioned above. In 40 nm technology, the 3D wrapper with wide-IO DRAM support occupied 0.025mm2, negligibly small for a realistically sized SOC. The tool flow is available in alpha release for selected customers from Cadence Design Systems.

 

References

1. E.J. Marinissen et al. "A Structured and Scalable Test Access Architecture for TSV-Based 3D Stacked ICs," IEEE VLSI Test Symposium, April 2010, Santa Cruz, California, pp. 269-274.

2. E.J. Marinissen et al. "3D DfT Architecture for Pre-Bond and Post-Bond Testing," Proceedings of IEEE International 3D Systems Integration Conference, November 2010, Munich.

3. E.J. Marinissen et al. "A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper," Journal of Electronic Testing: Theory and Applications, vol. 28, No. 1, February 2012, pp. 73-92.

4. E.J. Marinissen et al. "Automated Design-for-Test for 2.5D and 3D SICs., Chip Scale Review, September-October 2011, pp. 18-22.

5. S. Deutsch et al. "Automation of 3D DfT Insertion," Proceedings of IEEE Asian Test Symposium, November 2011, New Delhi, pp. 395-400.

6. IEEE 3D-Test P1838 Working Group, http://grouper.ieee.org/groups/3Dtest/

7. R. Goering, "Three Die Stack — A Big Step ‘Up’ for 3D-ICs with TSVs," in Cadence Community Blogs, December 2011 (see http://www.cadence.com /Community/blogs/ii/archive/2011/12/13 /three-die-stack-a-big-step-up-for-3d-ics-with-tsvs.aspx).

8. "ST-Ericsson and CEA-Leti’s WIOMING Prototype Shows How To Combine Wide IO Memory and Logic SoC for Future 3D Multi-Processor Architectures," Yole Développement 3D Packaging Newsletter, (22):16—18, February 2012 (see http://www.imicronews.com/ upload%5Cnewsletter%5C3DPackaging_Feb2012_iMN.pdf).

9. Wide I/O Single Data Rate (JEDEC Standard JESD229). JEDEC Solid State Technology Association, December 2011. http://www.jedec.org.

 

About the Authors

imec

Erik Jan Marinissen — Principal Scientist; Leuven, Belgium

 

Cadence Design Systems

Sergej Deutsch — former Cadence resident at imec; currently Ph.D. student at Duke University, Durham, N.C.

Brion Keller — Senior Architect; Endicott, N.Y.

Vivek Chickermane — Distinguished Engineer/R&D Director; Endicott, N.Y.

Subhasish Mukherjee — Senior Member of Consulting Staff; Noida, India

Navdeep Sood — Senior Application Engineer; Noida, India n

 
 
Search



Published By:
?¡Àcheap #167
38 Miller Ave.
Mill Valley, CA 94941
www.mazikmedia.com
converse@mazikmedia.com
Disclaimer | Privacy Policy