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Thermo-compression Bonding Process Window Compatible With 3D Wafer Stacking and Stability
(10/25/2012) Future Fab Intl. Issue 43
By H.Y. Li, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)
L. Peng, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)
F.X. Che, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)
C.S. Tan, Nanyang Technological University, Singapore
G.Q. Lo, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)
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An Optimal Cu-to-Cu Thermo-compression Bonding Process Window Compatible With 3D Wafer Stacking and Stability

H.Y. Li,1 L. Peng,1,2 F.X. Che,1 C.S. Tan,2 G.Q. Lo1

1Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Singapore 2Nanyang Technological University, Singapore


The Cu-Cu thermo-compression bonding process being compatible with 3D integration is important since all aspects of the FEOL, TSV, BEOL, back-side metalization and assembly processes need to be considered. Bonding temperature and force are critical parameters during Cu-Cu bonding. A high bonding temperature induces high TSV stress in the Si substrate; meanwhile, high contact resistance and its instability are observed when the bonding temperature is <300 °C, according to our study. Therefore, bonding temperature of 300 °C is suggested for Cu-Cu bonding and applied for 3D-IC stacking.


Cu-Cu thermo-compression bonding is a promising technology for 3D wafer stacking. Reports on Cu-Cu thermo-compression bonding have attracted significant attention.[1-3] Specifically, electrical and reliability results of 200 °C direct bonding were reported by Di Cioccio et al.[3] Cu-Cu thermo-compression bonding is critical technology to address the

Table 1. Parameters Used in Thermal Stress Simulation

ever-scaling requirement of the bump pitch in order to increase the bump density. The important applications of Cu-Cu bonding include direct Cu-TSV bonding with Cu-pad to form 3D interconnect.[4-7] However, high-temperature Cu-Cu bonding during 3D wafer stacking can reduce negative impact on the process integration; for instance, with temporary bonding resulting in de-bonding during the back-side CVD, PVD and metalization.

Figure 1. Thermal-stress Distribution When Heat and Pressure Are Applied and Hold at High Bonding Temperature

Cu-Cu bonding conditions are critical for the devices with Cu-TSV in via-middle (VM) implementation. Cu-Cu bonding is performed after devices and Cu-TSV fabrication. Therefore, bonding temperature and pressure are applied on the Cu-TSV and active device as well. Thermal stress from TSV affects the active device in the nearby surrounding Si significantly. The bonding condition is known to affect the keep-out-zone (KOZ) between TSV and devices around.[7] Thus, the bonding temperature has been identified as the primary contributor to the buildup of TSV thermal stress compared with bonding pressure.[7] Therefore, Cu-Cu thermo-compression bonding temperature is an important parameter to be considered in the context of 3D process integration.

Bonding Conditions and Effects on Embedded TSV

High bonding force and temperature are required to ensure the bonding quality and site-to-site uniformity. However, the bonding temperature and force are loaded on Cu-TSV as well. As a result, TSV generates thermal stress in Si substrate during bonding process. The thermal stress presents challenges during subsequent wafer processes such as back-grinding and TSV via reveal. Therefore, simulation of bond-ing force and temperature is necessary to guide the 3D process integration. The thermal stress in Cu-TSV (Φ: 5 µm, H: 30 µm) from Cu-Cu thermal-compression bonding is simulated by ANSYS. The simulation considers temperature ramp-up, applied pressure, high temperature dwell, pressure removal and cooling down to room temperature. The major parameters used are shown in Table1.

Figure 2. Simulation Results of Cu-Cu bonding at 60 kN for 1 Hour Held at Different Temperatures

The maximum stress is concentrated around the TSV bottom corner area when heat and pressure are applied and held at high temperature. The result is illustrated in Figure 1. A second high stress is distributed in the Si substrate near TSV bottom. When the top bonded wafer was thinned down to this area by the back-grinding system, complicated mechanical stress easily induced wafer crack. The maximum stress near TSV in Figure 1 is not symmetric, which increases the via-revealing process challenge.

Figure 3. Simulation Results of Cu-Cu Bonding at 300 °C (1 hour) With Different Bonding Forces

Extremely high thermo-mechanical stress could cause the Si substrate to crack. The stress weak point near the TSV bottom could affect wafer back-side thinning and via reveal. A previous study[8] showed that the bonding yield is improved with both the bonding force and the temperature. Therefore, it is essential to identify and select a Cu-Cu bonding process that results in the least-TSV-induced thermo-mechanical stress in the Si substrate. The maximum thermo-mechanical stress in the Si area near the TSV bottom is simulated for Cu-Cu bonding process at 200, 250, 300, and 350 °C with 60 kN bonding force. The maximum stress distribution during the bonding process is shown in Figure 2.

As shown in Figure 2, the Si-substrate is under high stress when the respective bonding temperature is applied, which is reduced during the cooling step. As expected, a higher bonding temperature results in higher stress. However, there is no significant variation in the stress value when the bonding pressure is applied, saturated at high temperature and removed within individual bonding process. Therefore, it is clear that the bonding temperature plays a significant role in the Si substrate stress buildup.

To further understand the role of bonding pressure, the simulation is repeated at 300 °C for 10, 30 and 60 kN of bonding force, and the results are shown in Figure 3. As can be seen, the maximum Si stress has no significant dependency on the bonding force. Again, based on an earlier study,[8] the bonding force merely increases the contact area to improve the overall bonding quality.

Figure 4. (a) Cross-bar Kelvin Structures Schematic; and (b) After Top Si Removal

The conclusion drawn from the simulation results on the dependency of the maximum Si stress level in response to bonding temperature concurs with the earlier report.[7] One guideline is to reduce the bonding temperature while maintaining a reasonable level of bonding force in order to obtain optimum bonding quality. The next section investigates and identifies suitable Cu-Cu bonding temperature for 3D process integration.

Impact on Cu-Cu Contact Resistance and Its Stability

200 mm Si-(100) wafers with two layers of single damascene Cu are used for wafer-on-wafer face-to-face stacking. Self-assembled monolayer (SAM)[9] is coated on a Cu bonding pad after a top dielectric recess that reduces the Cu oxidation effect. SAM is desorbed before Cu-Cu thermo-compression bonding. A cross-bar Kelvin structure is used to characterize the effect of bonding temperature on the contact resistance as shown in Figure 4. This structure can overcome wafer-to-wafer misalignment during contact resistance study. The top and bottom metal line width is 5 µm.

The bonding process is performed at 225, 275 and 300 °C, respectively, with 60 kN bonding force for one hour. The Cu-Cu thermo-compression bonding contact resistance is characterized by a four-point measurement. The contact resistance is ~5, 3.5 and 2.3 mW for bonding temperature at 225, 275 and 300 °C, respectively. As clearly shown in Figure 5, lower contact resistance is achieved when higher bonding temperature is applied.

Figure 5. Cu-Cu Contact Resistance Due to Bonding Temperature and Its Reliability

Cu-Cu contact resistance reliability is investigated by thermal cycle test (TCT). The sample is subjected to thermal cycling test with the temperature ranging from -40 °C to 125 °C. The ramp-up/down rate is ~15 °C/min and each thermal cycle is ~52 min. The Cu-Cu contact resistance is measured after 200 and 500 thermal cycles. The Cu-Cu contact resistance is consistent after 200 and 500 cycles of TCT when bonding is done at 300 °C. However, fluctuation in the contact resistance is observed for Cu-Cu contact bonded at 225 °C and 275 °C after TCT. Therefore, 300 °C is selected as the Cu-Cu thermo-compression bonding temperature in our bonding study. This bonding temperature can provide stable contact resistance.


In this study, it is noted that when the bonding temperature is <300 °C, higher resistance and unstable contact resistance are observed from the thermal cycling test. Meanwhile, increased bonding pressure can improve bonding yield and quality.[8] Therefore, Cu-Cu bonding temperature at 300 °C is chosen along with 60 kN of bonding force based on this study. In addition, surface pre-treatment with SAM is applied to achieve fine-pitch Cu-Cu interconnects bonding for wafer-on-wafer stacking.


1. R. Taibi et al. "Investigation of stress induced voiding and electromigration phenomena on direct copper bonding interconnects for 3D integration," in IEDM Tech. Dig., 2011, pp. 135-138.

2. Y.H. Hu et al. "Cu-Cu Hybrid Bonding as option for 3D IC stacking," IITC 2012, pp. 1-3.

3. L. Di Cioccio et al. "200°C direct bond-ing copper interconnects: electrical results and reliability," IEEE 3D Systems Integration Conference, 2011, pp. 1-4 (9-8)

4. Y.H. Hu et al. "3D Stacking Using Cu-Cu Direct Bonding," IEEE 3D IC 2011, pp 1-4 (1-3).

5. Cedric Huyghebaert et al. "Cu to Cu interconnect using 3D-TSV and Wafer to Wafer thermo-compression bonding," IITC 2010, pp. 1-3.

6. W.H. The et al. "Recent Advances in Submicron Alignment 300mm Copper-Copper thermocompressive Face-to-Face Wafer-to-Wafer Bonding and Integrated Infrared, High-Speed FIB Metrology," IITC 2010, pp. 1-3.

7. Chukwudi Okoro et al. "Analysis of the Induced Stresses in Silicon During Thermocompression Cu-Cu bonding of Cu-Through-Vias in 3D-SIC Architecture," IEEE ECTC 2007 pp. 249-255.

8. H.L. Leong et al. "Application of contact theory to metal-metal bonding of Silicon wafer," J. Applied Physics 2007 102 p. 103510.

9. D.F. Lim et al. "Achieving low temperature Cu to Cu diffusion bonding with self-assembled monolayer (SAM) passivation," IEEE 3DIC, 2009.


About the Authors

H.Y. Li - Scientist, Institute of Microelectronics

L. Peng - Ph.D. student, Nanyang Technological University and Institute of Microelectronics

F.X. Che - Scientist, Institute of Microelectronics

C.S. Tan - Assistant Professor, Nanyang Technological University

G.Q. Lo - Deputy Executive Director, Institute of Microelectronics


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