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450 mm Era: A New Opportunity for the Semiconductor Industry
(4/25/2013) Future Fab Intl. Issue 45
By John Lin, G450C
Paul Farrar, G450C
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The Global 450 Consortium (G450C), announced by New York Governor Andrew M. Cuomo in September 2011 and headquartered at the SUNY College of Nanoscale Science and Engineering (CNSE) in Albany, is leading the industry transition from the 300 mm wafer to 450 mm wafer production.

450 mm Era: A New Opportunity for the Semiconductor Industry

John Lin, Paul Farrar

The Global 450 Consortium (G450C), announced by New York Governor Andrew M. Cuomo in September 2011 and headquartered at the SUNY College of Nanoscale Science and Engineering (CNSE) in Albany, is leading the industry transition from the 300 mm wafer to 450 mm wafer production. This first–of–its–kind collaboration includes five leading international IC manufacturing companies partnering with CNSE to create the next generation of computer chip technology. The G450C program integrates key semiconductor IC makers with important equipment and material suppliers, along with the investment from New York State and the vision and leadership of Governor Cuomo.

Why 450 mm? Reduce manufacturing cost, stimulate another wave of innovation on equipment and manufacturing methods, and drive toward greener manufacturing.

Semiconductor manufacturing costs have increased rapidly as technology complexity has accelerated at sub–20 nm nodes (Figure 1). Process steps such as multiple patterning, EUV lithography, 3D transistors, channel engineering, atomic–layer deposition (ALD) and novel backend technologies have added costs. Evolving technology drives the need for periodic wafer size increases to maintain historical cost reduction trends.

Figure 1. Node–to–node wafer cost increases signigicantly because of technology complexity.

Wafer size transitions have historically occurred on about a 10–year cycle. As pictured in Figure 2, the 300 mm node has lasted longer as the leading–edge production node than previous generations. Thus, the transition to 450 mm wafers late in the decade is already later in relation to previous transitions. The 450 mm wafer ramp is now expected to be in 2017–2018 for early adopters.

Figure 2. History of wafer capacity for each wafer size transition.

The 450 mm Benefits

On average, a 30% cost reduction was seen with the implementation of 300 mm wafers from the previous 200 mm cost basis. Some semiconductor manufacturers reported even greater cost benefits. The industry consensus is that the 450 mm wafer can provide similar cost reduction opportunities.

The cost and performance advantage from the manufacturing productivity enabled by the 450 mm transition will allow the semiconductor industry to continue to migrate to advanced technology nodes, and with significant cost improvements over technology nodes. This will be a key component of maintaining Moore's Law. The semiconductor industry's historic cost reductions have enabled the mobile and interconnected society we live in.

The 450 mm wafer transition provides a great opportunity to stimulate and implement another wave of innovations on equipment performance. Improvements in uniformity, productivity, process control, automation and manufacturing systems will be required to achieve these cost benefits. Figure 3 illustrates the productivities that were achieved with the 300 mm wafer introduction.

Figure 3. Many innovations enabled 300 mm transition with significant productivity and engineering improvements.

Another benefit of the implementation of the 450 mm wafer will be to create new opportunities to achieve a more environmentally friendly semiconductor manufacturing process. During the 300 mm transition, the use of energy, water, chemicals and emissions per unit wafer area were significantly reduced (Figure 4). Besides simply using smaller amounts of water, chemicals and energy in relation to the larger wafer area, the G450C has also set early targets and recommendations for the use of these items. This is being done early in the cycle compared with the 300 mm transition. The industry is targeting a 30–40% per area saving for 450 mm wafers.

Figure 4. The 300 mm transition showed considerable improvement from a green perspective.

The G450C Program

To speed up the 450 mm transition, three major IC makers (Intel, Samsung and TSMC) reached an agreement in 2008 to collaborate on industry infrastructure development, and to share the industry tool development cost. More importantly, the collaboration would lead to a synchronization of tool suppliers' schedules, reducing the risk of high development costs, establishing standards, providing test wafers, and shortening the tool development cycles. The three IC makers continued the collaboration to purchase silicon wafers in 2009, and to acquire metrology tools, stockers and initial prototype tools.

In September 2011, Governor Cuomo announced that the G450C would be established at CNSE. The 450 mm tools will reside in the newly built NanoFab Xtension (NFX, Figure 5). The facility was ready for equipment in February 2013, with 280,000 ft2 floor space and 60,000 ft2 cleanroom. G450C will use the state–of–the–art capabilities established at CNSE for joint development activities and to support a comprehensive industry ecosystem.

Figure 5. The 450 mm fab in the NanoFab Xtension (NFX) at CNSE.

Five semiconductor member companies–Intel, Samsung, TSMC, IBM and GLOBALFOUNDRIES–are working in partnership with CNSE. The G450C program is a public–private partnership that will develop equipment prototypes and high–volume manufacturing (HVM) tools, and establish a coordinated test, metrology and wafer program to enable a cost–effective industry transition to 450 mm wafers. In summary, this will synchronize industry efforts by involving the key stakeholders in setting a clear development roadmap and implementation timeline.

The G450C program has established a platform of key objectives. Initially, in the 2012–2014 timeframe, the team is focused on supporting supplier tool development with test wafer capability. Key metrics have been established for defect density, uniformity, and system reliability and productivity. The program will demonstrate these capabilities using 14 nm (nominal/ITRS half–pitch) unit processes. In the 2015–2016 timeframe, the focus will be on improving tool performance to support customers' expectations for pilot operations. It is expected that the 450 mm toolset will be continuously improved to enable high–volume manufacturing in the 2017–2018 timeline.

The G450C program staff comprises engineers from CNSE and from each member company. The expertise of the engineering staff will allow for effective collaboration with the equipment companies' engineering teams to manage a successful tool demonstration and qualification at the 14 and 10 nm nodes. This unique collocation of equipment and semiconductor companies' skills will pave the way to a successful industry transition to 450 mm.

Another aspect to the program is to enable early standardization of nonproprietary components in the facility and equipment. The G450C team is working with SEMI and its members on these pre–competitive supplier–identified projects.

Tool and Wafer Challenges

The G450C team is driving hard on tool and process performance, and has published equipment performance metrics (EPM)–tool specification targets for equipment with design–in capability as agreed upon with suppliers–as well as guidance on ESH, facilities requirements and standards compliance. Figure 6 shows the EPM for a representative etch application. The complete EPM for the 450 mm toolset to be demonstrated during the program using standard demonstration test methods (DTMs) is available on the G450C website (www.g450c.org).

Figure 6. An example of equipment performance metrics (EPM).

The selection of 450 mm tools has been accomplished. Equipment will be moved in and installed between 2013 and 2014, according to the defined schedules. There are about 60 tools that will be tested for ˜100 applications to meet the 14˜10 nm specs. These tools allow G450C to investigate a full spectrum of processes and measurement needs to ensure successful test wafer demonstration. This site will be the largest 450 mm test bed in the world. The tool ready timeline for each type of tool is shown in Figure 7.

Figure 7. The G450C 450 mm tool demonstration plan.

Lithography capability is one of the most strategic elements to ensure success in the 450 mm transition. G450C recognizes this critical factor, and is mobilizing resources to accelerate lithography tool development and delivery to G450C. The tool will likely be delivered to G450C in 2015 and HVM tools will be ready in 2017–2018. Automation is also a key for successful 450 mm process and production. G450C will implement automation hardware and software connecting tools in the fab and trace the entire wafer process to enable advanced control on equipment and processes.

The G450C team also continued the previous effort to drive the wafer quality. Silicon manufacturers have been able to produce wafers meeting M74 mechanical handling wafer spec in 2011. They are committed to meet the M76 monitoring wafer spec by 2013 and meet the M1 prime wafer spec in 2014.

To lower development costs, G450C offers a wafer loan program to the 450 mm community. This allows tool suppliers to obtain high–quality wafers for tool development, with substantial discounts in wafer cost. G450C will also offer metrology assistance and process capability to provide measurement and materials needed for tool development. The program goal is to provide cost–sharing opportunities to assist tool suppliers.

G450C is representative of all industry constituencies–the Management Council includes executives from all chipmaker member companies, CNSE and suppliers through its associate members and SEMI. G450C is also coordinating with EEMI450 entities in Europe, Metro450 in Israel, and the SEMI Equipment Supplier Group in Japan to avoid duplicated effort and address issues through global collaboration.

Roadmap and Future Efforts

G450C has coordinated industry collaboration through member companies representing IC manufacturers, equipment suppliers and their suppliers, a facility group, and material suppliers. This serves to align the timeline for tool installation and demonstration between 2012 and 2014, with the majority of suppliers providing early production tools for IC makers' pilot lines in 2015.

The wafer development is on schedule, with the M1 wafer to be ready in 2014. Illustrated in Figure 8, the readiness of high–volume manufacturing is driven by lithography development, with the schedule on track for 2017–2018.

Figure 8. The 450 mm development roadmap.

About the Authors

John Lin

John Lin, an assignee of TSMC, was appointed vice president and general manager of operation of G450C in March 2012. Prior to joining G450C, he was director of TSMC's Manufacturing Technology Center, and has held various manager positions in semiconductor technology development and manufacturing. Lin holds 59 U.S. patents and is author/co–author of 25 papers. He received his Ph.D. in optoelectronics from the University of Oxford. He won the award of Outstanding Contribution Engineer from the president of Taiwan in 2008

Paul Farrar

Paul Farrar was appointed general manager of G450C and CNSE vice president for manufacturing innovation in September 2012. Prior to his appointment, he was vice president for strategic alliances for IBM Microelectronics. During his 34 years at IBM, Farrar held various executive positions in semiconductor process development, manufacturing, and product line management. He has a master's degree in materials engineering from Rensselaer Polytechnic Institute (RPI). n


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