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An Analysis of Lithography Solutions to 10 nm Logic Node and Beyond
(7/4/2013) Future Fab Intl. Issue 46
By Yayi Wei, GLOBALFOUNDRIES
David Cho, GLOBALFOUNDRIES
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Why 1.35 NA 193 nm immersion lithography plus double or triple patterning will still be the viable solution to critical layers in 10 nm node.

An Analysis of Lithography Solutions to 10 nm Logic Node and Beyond

Yayi Wei, David Cho
GLOBALFOUNDRIES

Introduction

According to the International Technology Roadmap for Semiconductors (ITRS), the risk production of 10 nm logic devices is scheduled in 2015.[1] Ten nm logic device requires a critical poly pitch (CPP) of 64 nm and first metal half-pitch of 24 nm. An overlay control of < 5 nm (3s) and CDU (critical-dimension uniformity) control of < 2.2 nm (3s) are required in lithographic process. Assuming 0.7x scaling per node, 7 nm node will require a CPP of 45 nm, first metal half-pitch of 20 nm, overlay control of < 3.5 nm and CDU control of < 1.5 nm. Table 1 summarizes these parameters.

EUV Option

EUV development has a long history and has attracted a significant amount of resources. The most impacting point of EUV is its wavelength - 13.5 nm. This extreme short wavelength promises much better resolution than with 193 nm immersion lithography. Because the Rayleigh k1 value when printing with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193 nm immersion lithography, the process windows with EUV lithography are wide.[2] EUV lithography is also expected to result in a significant reduction of manufacturing costs because of the lower mask counts and because a smaller number of process steps required.

Table 1. Lithographic Requirements for 10 nm and 7 nm Logic Devices

The insertion point of EUV lithography into manufacturing was originally planned at 14 nm logic node. Extensive evaluations from end-user perspectives have occurred in development alliances both at Albany Nanotech[2] and imec.[3] These evaluations focus on current status of key performance metrics including scanner throughput; mix-and-match overlay between EUV and 193 immersion scanners; process introduced defectivity; defect count in mask blanks; and resist performances. Table 2 shows the combined results of these evaluations. The requirements for 10 nm node are also listed in Table 2 for comparison and identification of the gaps.

As seen in Table 2, the major gap is in throughput, due to insufficiency in EUV source power. The lack of sufficient machine throughput may disqualify the EUV process from being used in 10 nm mass manufacturing. There is also a clear gap between the current mask blank defect count and manufacturing requirement. These gaps have been well recognized by the entire EUV community. A CO2-Sn-LPP EUV light source with a high power of
> 200 W is being developed,[4] and various techniques to mitigate the mask blank defects have been proposed.[5]

Equipped with a new and powerful source, EUV scanner suppliers have designed so-called production tools. These production tools promise much better performance than the tools (so called pre-production tools) evaluated at the aforementioned alliances. For example, it can achieve a throughput of 60 WPH. However, the omission of 14 nm and 10 nm insertion points means the new tool must face the challenges of 7 nm requirements. It remains to be seen if EUV development can catch the pace of technology.

Table 2. Current Status of EUV Lithography Performance

A practical approach to early introduction of EUV into production, perhaps, is to use it for contact or via layers. Most contact and via levels can be exposed with EUV lithography using a single exposure, while patterning these levels with 193i lithography generally requires pitch splitting and multiple masks. Furthermore, contact and via levels have a lower pattern density, which means that defect avoidance by means of pattern shifting can be used to fabricate defect-free EUV masks for these levels from blanks with a small number of multilayer defects.[2]

Multiple Electron-Beam Exposure

Electron-beam (e-beam) lithography uses well-focused e-beam to expose the resist. The primary advantage of e-beam lithography is that it is one of the ways to beat the diffraction limitation of light and achieve features in the nanometer regime. A structure of < 20 nm was demonstrated in the early 1990s. The key limitation of the e-beam lithography is throughput - it may take several days to expose an entire wafer with a single electron beam. A long exposure time leaves the user vulnerable to beam drift or instability during the exposure. So far, e-beam lithography is only widely used in the mask making industry and in small field device research organizations.

Recent progress on multiple e-beam systems (also called maskless lithography, ML2) opens new hope on solving the throughput bottleneck. In the 2009 ITRS roadmap, ML2 is the third option for 22 nm and 16 nm half-pitch nodes (somehow equivalent to 10 nm and 7 nm logic nodes) after EUV and 193i double-patterning.

Multiple e-beam lithography exposes wafers with multiple e-beams (hundreds or thousands of beams) simultaneously. The massive parallelism is expected to overcome the throughput limitation of a single e-beam system. Various technical approaches have been explored to realize the massive parallel beams.[6] Among them, Mapper and KLA-Tencor have already had their alpha tools evaluated by IC manufacturers and have their own approach and roadmaps.[7] Mapper's alpha tool has 110 beams (i.e., columns). Their roadmap is to develop beta-tool, which inserts 7x7 aperture arrays in each column, forming 7x7 sub-beams. Each sub-beam can be individually controlled. The throughput of the beta-tool is designed to be 10-20 WPH. Each beta-tool has a footprint of 1 square meter. Ten beta-tools can form a group and work with one track to achieve 100 WPH. The total footprint of 10 beta-tools is similar to a 193 nm immersion scanner.[8] KLA-Tencor has a different approach: so-called reflective e-beam lithography (REBL). The illumination e-beam from an obliquely oriented electron gun is bent to incident on a dynamic pattern generator (DPG) at a normal angle and is decelerated to a very low voltage. The DPG is a CMOS ASIC chip and contains an array of small independently controllable electrostatic lens elements, which act as an array of electron mirrors. In this way, the REBL system is capable of writing patterns using massively parallel exposure by ˜1 million pixels.[9]

All these exposure systems show potential for high resolution and high throughput. Evaluation of these systems is ongoing in the semiconductor manufacturing fabs.[7] However, the overall performance data is still limited, and its throughput is still lower than EUV. Even with the best available system, it still takes hours to expose an entire wafer. Another concern is the mix-and-match alignment accuracy between the e-beam exposure and optical exposures. Can it achieve < 5 nm overlay? The answer is probably no. Thereby, it is less likely that the multiple e-beam lithography can be used in 10 nm and 7 nm nodes. It is worth mentioning that the e-beam lithography does not require a mask, as the pattern is generated by controlled e-beam exposures. This is extremely attractive, because the mask cost in advanced technology nodes increases exponentially. This unique advantage ought to be taken in some situations. Recently, researchers have proposed that e-beam lithography can be pursued as a complementary solution to 193i for patterning critical layers. The feasibility of complementary lithography using 193i and e-beam lithography in a mix-and-match approach has been demonstrated.[10]

Nanoimprint

Nanoimprint lithography (NIL) has a simple concept. A resist-coated surface is embossed by a template. After the template is lifted, the pattern remains in the resist film. A popular process flow is called step and flush imprint lithography (SFIL), proposed by Molecular Imprints.[11] The template is made from a standard photomask blank and the patterns in the template are obtained by using the same technology for phase shift mask fabrication. First step: an array of low viscosity pico-liter-sized drops imprint resist is spread across the field in the wafer. Second step: with the template pressing down, capillary action draws the resist into the template features. Third step: once the pressing is completed, ultraviolet (UV) light, passing through the glass template, is used to cross-link the resist and convert it to a solid. Last step: the template can then be withdrawn.

NIL has demonstrated a resolution capability of < 20 nm half-pitch with excellent CDU and line edge roughness. Since the patterning is directly formed from the template without development, the wafer CDU is almost equivalent to pattern CDU in the template. A CDU of 1 nm (3s) is expected to be achieved. However, the challenge of bringing NIL into mass production for 10 nm node and beyond mainly is its high process defectivity and poor overlay control.[12] The defects can be originated from the imprint process and from the template. They are classified as the non-fill defect (resist does not fill the template well and bubbles are entrapped); the template defect (defects in template); and the plug defect (generated by tearing away imprinted resist when a template is separated from wafer). Reduction of these defects requires improvements on the equipment, material, template fabrication technology, and defect inspection infrastructures. Defectivity control for NIL is very challenging, as the printing magnification between template and wafer is 1 to 1. NIL has no projection lenses and almost all overlay errors are from wafer distortion and pattern distortion in the template. Researchers from Toshiba reported an overlay of 10 nm, which is still too far behind the requirement for 10 nm logic node.

Directed Self-Assembly

Directed self-assembly (DSA) has attracted great attention in recent years. The self-assembly process is controlled by weak molecular interactions between block copolymers, such as van der Waals and capillary forces, p - p interactions, and hydrogen bonds. Pattern dimensions in turn are controlled by the molecular size and by the magnitude of the interactions. The characteristics of self-assembly differ substantially from those of the conventional lithography process. The conventional lithographic process outcome is controlled by kinetics (e.g., acid-catalyzed de-protection and acid diffusion in chemically amplified resists, and dissolution kinetics during development of the relief image).[13]

The exquisite dimensional control at nanometer-scale feature sizes is one of the most attractive properties of block copolymer self-assembly. Features with nanometer sizes can be easily formed with the self-assembly approach. At the same time, device and circuit fabrication for the semiconductor industry requires accurate placement of desired features at irregular positions on the chip. Directed self-assembly - the use of topography to direct the self-assembly - has shown great promise in solving the placement problem.[14] The topography used for directing the self-assembly has large scale and can be generated by conventional lithography. However, the main concern for the commercialization of DSA for semiconductor or manufacturing is defectivity. Current DSA activities are mainly in research phases and progress yet to be seen.

Summary

The status of all alternative lithographic solutions (other than 193 nm immersion) has been reviewed in previous sections. None of them is ready for 10 nm logic node. Therefore, 1.35 NA 193 nm immersion lithography plus double or triple patterning will still be the viable solution to critical layers in 10 nm node. Since double patterning with 193i exposure was first introduced in 20 nm node, significant amount of knowledge - in terms of how to handle the pattern split, alignment strategy and defect control - has been accumulated. The technical challenges to this approach are minimal, although it is obviously not a cost-efficient solution. EUV may be able to be used for 7 nm node.

References

International technology roadmap for semiconductors, edition 2011

  1. O. Wood et al. "Insertion Strategy for EUV Lithography," Proc. of SPIE vol. 8322, 832203 (2012)
  2. J.V. Hermans et al. "Progress in EUV Lithography Towards Manufacturing from an Exposure Tool Perspective," Proc. of SPIE Vol. 8322, 832202 (2012)
  3. J. Fujimoto et al. "Development of laser-produced plasma based EUV light source technology for HVM EUV lithography," Proc. of SPIE vol. 8322, 83220F (2012)
  4. R. Teki et al. "Alternative Smoothing Techniques to Mitigate EUV Substrate Defectivity," Proc. of SPIE vol. 8322, 83220B (2012)
  5. K. Ronse, "E-beam Mask-less Lithography: prospects and challenges," Proc. of SPIE vol. 7637, 76370A (2010)
  6. B.J. Lin, "Future of Multiple-E-Beam Direct-Write System," Proc. Of SPIE vol. 8323, 832302 (2012)
  7. M.J. Wieland et al. "MAPPER: High throughput maskless lithography," Proc. of SPIE vol. 7637, 76370F (2010)
  8. R. Freed et al. "Reflective electron-beam lithography: progress toward high throughput production capability," Proc. of SPIE vol. 8323, 83230H (2012)
  9. C. Hohle, "E-Beam Direct Write on 300 mm Wafers: Maskless Patterning for Various Applications," Future Fab Intl., Issue 42 (2012)
  10. M. Smith, http://www.molecularimprints.com/pdf/Tech_Litho_Beyond_32 nm.pdf
  11. T. Higashiki et al. "Nanoimprint Lithography for Semiconductor Devices and Future Patterning Innovation," Proc. of SPIE vol. 7970, 797003 (2011)
  12. W. Hinsberg et al. "Self-Assembling Materials for Lithographic Patterning: Overview, Status and Moving Forward," Proc. of SPIE vol. 7637, 76370G (2010)
  13. H.-S.P. Wong et al. "Block Copolymer Directed Self-Assembly Enables Sublithographic Patterning for Device Fabrication," Proc. of SPIE vol. 8323, 832303 (2012)

About the Authors

David Cho

David Cho is a director of Process Engineering at GLOBALFOUNDRIES, where he leads the Lithography group in advanced module technology development. He previously worked at Samsung Austin Semiconductor. David earned his M.S. in chemical engineering at the University of Michigan.

Yayi Wei

Yayi Wei is a principal member of the technical staff with GLOBALFOUNDRIES. He received his M.S. in engineering from the Electronics Institute, Chinese Academy of Sciences, Beijing, in 1992, and his doctoral degree from the Max-Planck-Institute for Solid-State Research, Stuttgart, in 1998. Dr. Wei worked in the Oak Ridge National Laboratory on electron-beam lithography and nano-fabrications. In 2001, he joined Infineon Technologies and participated in the process development and material evaluation of advanced lithography in 193 nm, 157 nm, 193 nm immersion and EUV. He joined GLOBALFOUNDRIES in 2009 and served as a senior member of the technical staff, investigating advanced lithography processes and materials. Dr. Wei has published numerous works and holds several patents in the field of lithography.

 

 
 
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