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Development and Implementation of 300mm Cu CMP Manufacturing Systems
(2/2/2002) Future Fab Intl. Issue 12
By R. Tiwari, Texas Instruments Incorporated
M. Soucek, Texas Instruments Incorporated
Joel Strupp, Texas Instruments Incorporated
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Advanced interconnect technologies using copper as the interconnect material of choice along with a variety of dielectric materials were also planned for rapid implementation on 300mm wafers. In fact, Cu CMP has emerged as a critical back-end-of-the-line (BEOL) processing step for advanced interconnect technologies and has posed a serious challenge for 300mm production. In the 300mm Cu process flow, given the increased cost of ownership, there exists a need for Cu CMP process that meets the low topography requirements of multi-level damascene structures while meeting IC device performance requirements.

Morrison et al have previously described the commonly practiced Cu CMP process[1]. It is a two-step approach utilizing at least two slurries. In the first step, the main goal is to ensure the complete removal of the deposited copper. This step is terminated using an endpoint scheme. The copper removal step ends with an over polish step to account for the non-uniformity of the deposited copper thickness profile and the inherent non-uniformity of the copper removal during the CMP process. The removal rate profile, endpoint algorithm and over polish step together significantly influence the device performance by affecting the metal line resistance.

Advanced interconnect technologies using copper as the interconnect material of choice along with a variety of dielectric materials were also planned for rapid implementation on 300mm wafers. In fact, Cu CMP has emerged as a critical back-end-of-the-line (BEOL) processing step for advanced interconnect technologies and has posed a serious challenge for 300mm production. In the 300mm Cu process flow, given the increased cost of ownership, there exists a need for Cu CMP process that meets the low topography requirements of multi-level damascene structures while meeting IC device performance requirements. The additivity of topography with every subsequent metallization level poses serious challenges on Cu CMP process capability. Intermediate dielectric planarization is frequently used to eliminate topography created during Cu CMP. This additional step adds cost and negates one of the potential advantages of dual damascene processing.

Copper CMP Process

Morrison et al have previously described the commonly practiced Cu CMP process[1]. It is a two-step approach utilizing at least two slurries. In the first step, the main goal is to ensure the complete removal of the deposited copper. This step is terminated using an endpoint scheme. The copper removal step ends with an over polish step to account for the non-uniformity of the deposited copper thickness profile and the inherent non-uniformity of the copper removal during the CMP process. The removal rate profile, endpoint algorithm and over polish step together significantly influence the device performance by affecting the metal line resistance.

The second step of the Cu CMP process following the copper removal involves the removal of barrier metal. This is very important for the development of multi-level copper interconnect devices. Practically, it is very difficult to have barrier slurry that does not have measurable dielectric and/or copper removal rates. Based on the relative removal rates ratio of the Copper and dielectric, the barrier slurries may be classified as (a) High selectivity slurry, and (b) Low selectivity slurry. This step has a corrective role in modifying the post-copper removal topography, in most cases beneficially.

It was mentioned at the very outset that low CMP topography is an essential requirement for multilevel damascene technology processing. This is to eliminate the intermediate dielectric planarization that may be needed to reduce topography resulting from the Cu CMP process. The copper removal slurries are highly selective to Cu compared to the dielectric or barrier removal. The conclusive step of over-polish during Cu removal, prior to the barrier CMP, then leads to complete copper metal removal. However, this causes metal dishing in wide structures and copper recess in dense structures. It is at this juncture that the removal rate ratios of the copper and dielectric in the barrier slurry can influence the final topography. Along with the barrier removal, there occurs a topography correction to the extent determined by the dielectric and copper removal rates of the barrier slurry and the duration of polish. In the case of the high selectivity barrier slurry, the topography correction is achieved primarily by the reduction of the dielectric step heights in the vicinity of the copper lines (isolated or dense). The copper metal thickness remains predominantly unchanged. Conversely, in the case of the low selectivity approach, the metal thickness and the copper surface profile is also changed due to the measurable copper removal rates, along with the reduction in the heights of the dielectric regions. This yields a post-CMP topography that is amenable to the construction of multiple interconnect levels. This improved topography can also obviate the need for an additional ILD CMP step that needs to be undertaken to correct/improve the post Cu CMP topography. From the 300mm manufacturing perspective, this is significant for reducing costs that can be attributed to CMP.

Post-Cu CMP Clean

As in 200mm CMP manufacturing, the post-Cu CMP clean constitutes a critical step in 300mm Cu CMP manufacturing. Since 300mm manufacturing is limited to the mini-environment using the FOUP, there is no possibility of wet wafer handling and, as a result, a dry-in and dry-out operation is required for the 300mm CMP processing. In other words, integrated CMP cleaners are a requirement for 300mm CMP operations. In the case of Cu CMP, this requirement is further underscored by the risk of photo-induced diode corrosion (PIDC) of wet wafers. The integrated cleaner is useful as it eliminates the need for storage of polished copper wafers in corrosion inhibition baths prior to cleaning and minimizes the potential for the PIDC.

The actual practice of post-CMP clean can be an extension of the existing 200mm CMP version, upgraded for the increased diameter of 300mm wafers. Currently, the most common practices are non-contact cleaning using megasonic baths, or contact cleaning using brush scrubbers. The two approaches each have their strengths and weaknesses. The megasonic approach may be useful in particle removal in the narrow recesses of a polished Cu wafer, where the ability of the brush to reach the narrow recesses or ‘crevices’ may be limited. Similarly, the brush scrubbers might particularly be useful where the megasonic energy is unable to separate the particle that is physically attached to the copper metal surface. A combination of the non-contact and contact cleaning is currently being offered as a part of an integrated CMP system by Applied Materials for the 300mm Cu CMP cleaning process. This is advantageous as it offers the flexibility to use multiple cleaning chemistries for the megasonic and scrubber cleaning techniques.

Role of Consumables

In 300mm CMP manufacturing, consumables significantly impact the cost of ownership and process performance for Cu CMP processing. This increased cost of consumables is partly due to larger size, but also due to the infancy of the worldwide 300mm CMP market. In fact, Morrison et al have mentioned that for an average Cu CMP process, the cost of consumables constitutes 50-70% of the total process cost[1]. Additionally, amongst all the CMP processes, the effect of consumables on the process performance is most obvious in Cu CMP. In Cu CMP processing, the selection of polish pads and the polish slurry are the primary consumable variables influencing the post-CMP metrics of topography and defectivity. Polish pads are characterized by the pad texture and the physical characteristics. Pad texture is known to influence the slurry distribution on the pad surface during CMP, which in turn influences the copper removal behavior during the CMP process. Polish pads have been observed to affect the Cu removal rate, the removal rate profile and associated non-uniformity. This also has an import on the resultant metal surface defectivity. The physical characteristics of the pad i.e., material, density and thickness can also influence the global and local planarization that is achieved during Cu CMP.

The Cu removal rate, specifically, controls the wafer polish time on the polish pad. This directly influences the post-CMP topography, and indirectly the tool throughput, which influences the cost of ownership. The increased wafer polish time will lead to a center-to-edge variation in the Cu metal thickness due to the edge-fast or center-fast characteristic of the removal rate profile. This is undesirable for uniform device performance obtained across the wafer. Figure 1 is an example showing the difference in the Cu removal rate profile of 300mm wafers for two different pads at Texas Instruments, Dallas.

Figure 1. Effect of polish pad on the copper removal rate non-uniformity on a 300mm wafer. Radial position 1 corresponds to the wafer center.

Click figure to expand Click figure to expand
Figure 2. Example of incomplete Copper CMP polish showing (a) incomplete barrier CMP and (b) residual copper due to CMP process variations.

Cu CMP slurries are among the highest cost consumable chemicals in IC device manufacture. In 300mm CMP manufacturing, this is further additive to the increased equipment costs. These are typically multi-component slurries with a short shelf-life associated with the final mixed product. The CMP slurry can be classified on the basis of their role in the CMP process into two broad categories: (a) Cu polish slurry and (b) Barrier slurry. While the copper slurry market is by no means established, it is the mainstay of the polish process as it accounts for the bulk copper removal. The commercial slurry manufacturers each have identified the Copper CMP slurry as a growth market and continue to focus their efforts towards improving the manufacturability of the Cu CMP slurries. Significant progress has been achieved in improving the slurry settling behavior and planarization capability. However, all this has not led to any significant reduction in the cost of slurries. The cost considerations have also led several IC device manufacturers to develop Cu slurries that are adapted to their respective integrations, thereby achieving the requisite process performance along with reduced costs.

The barrier slurry also continues to be in an evolutionary phase, with each manufacturer trying to produce a barrier slurry that improves the post-CMP topography resulting from the copper removal step using their respective copper slurry. In the present scenario, wherein a multitude of copper slurries exist, the selectivity of the commercially available barrier slurry increasingly appears to be adaptable to suit each IC device manufacturer. The end focus in the barrier slurry development is to yield a topography that obviates the need for an intermediate dielectric planarization step.

Also, the slurry distribution systems are an integral part of the 300mm CMP manufacturing system due to the instabilities associated with the storage of these slurries. The main focus of the slurry distribution systems is towards minimizing the differences in the percent solids and chemistry between the points of distribution and use at the polisher. Another important aspect of the slurry distribution system is the filtration. Point-of-use filtration is the universally adopted method to minimize the most prevalent post-CMP defects (particles and scratches). Thus, the choice of filtration scheme also has a measurable process impact and constitutes a significant consumable cost. Inline slurry monitoring systems that measure the flow rate, specific gravity and percent solids are also very useful in achieving greater process control to give uniform time-based CMP performance.

Post-CMP Inspection.

The defect inspection following copper CMP is a critical point in the manufacture of copper-based interconnect devices. This is due to the fact that it can monitor the photolithography, etch, and deposition steps preceding the copper CMP step. Typically, four types of defect monitoring are used: integrated, darkfield, brightfield and e-beam. Integrated metrology in the CMP module has lower sensitivity than traditional inline monitor tools but has an extremely high sampling rate. The high throughput of the integrated metrology tools reduces risk to process excursions by minimizing the number of wafers affected. One macroscopic defect typically associated with the Cu CMP process is residual copper/barrier film due to incomplete polish. The location of these defects on the wafer is dependent on the actual CMP process, and can be reworked through the CMP process module. The overall CMP process yield can thus be increased. A development program undertaken at Texas Instruments in collaboration with Applied Materials has successfully yielded a technique, which can be integrated into the Cu CMP process loop to detect, identify and eliminate any post-Cu CMP residual metal or barrier. Figures 2a and 2b show the inspection profiles of incomplete polish, and partially polished wafers inspected using the developed technique. This inherent benefit of integrated metrology is distinct from the historical inline monitoring, which is typically done using slower bright-field and e-beam techniques. It has been shown that integrated metrology, when combined with traditional inline monitoring of high value devices, can enhance the detection capabilities of the inline monitors[2].

Bright-field inspection tools perform well at the post-CMP inspection due to excellent signal-to-noise, and are highly effective at detecting and tracking killer defects. Smaller pixel sizes and new light sources such as ultraviolet have allowed bright-field tools to increase sensitivity and capture rate for 130nm design rules and below. Typical killer defects detected are copper sidewall voids, corrosion, deep CMP scratches and deformed geometry. Figure 3 is a typical image of corrosion defect seen after Cu CMP. Non-killing defects that are potential reliability problems are small particles, shallow CMP scratches and small pits. Figures 4a and 4b show a small particle and scratches constituting non-killing defects. Control of the non-killing defects is essential to maintaining capture rate and effective classification of the critical, killing defects.

Figure 3. Typical image of corrosion defect seen after Cu CMP.

E-beam inspection has historically been a tool for process development learning and for major systematic defect detection of very small, sub-design rule physical defects. Advances in hardware and software have made it possible to use the technique for inline detection of voltage contrast defects in both array and logic areas. The e-beam inspection can be used for inline electrical defect, thereby enabling shorter development cycles and quicker ramp to yield entitlement. High kill ratios of these electrical defects enable matching to functional probe results, thereby allowing accurate yield prediction. Another added advantage of this technology, is that after process/product qualification, sample inspections on production material can allow a factory to monitor the copper process and reduce risk to yield loss or process reliability excursions.

Click figure to expand Click figure to expand
Figure 4. Non-killer (a) particle defects and (b) scratches seen after Copper CMP.

Inline dark-field inspection tools, using oblique and normal incidence, have higher sensitivity than typical integrated metrology tools, can detect a greater number of defect types, and are capable of a higher throughput than bright-field tools. The lower cost of ownership of these tools versus bright-field tools facilitates increased sample size, when investigating process issues such as wafer run order effects and chamber performance differences.

Common to all of these inspection types is the need for fast, accurate automatic defect classification. Once the process is stable and the majority of the systematic defects are eliminated, automatic defect classification can be employed to bin all of the defects of interest real-time during the inspection. The major advantage is quick determination of out of control lots based not just on defect counts but on killer defect types. This reduces response time to excursions and giving manufacturing engineers better data to address the process and/or equipment issues.

Conclusion

The development and implementation of a CMP manufacturing system for 300mm diameter wafers requires a quantum change in the adaptation of conventional 200mm CMP manufacturing practices. The increased material and equipment costs accompanying the greater than two-fold increase in the product output per wafer, necessitate a well-defined closed loop control system to monitor the numerous variables that can impact the copper CMP processing. Automated handling and process control along with inline post-CMP inspection protocols are imperative aspects of 300mm CMP manufacturing systems. In its current state of infancy, cost considerations need to be carefully weighed and relegated, if necessary, to achieve the desired process performance in 300mm manufacturing.

References

[1] W. Morrison, S. Joshi and R. Tolles, ‘Copper and STI CMP Technology: The Challenges and the Cost.’, Future Fab International, Issue 11, p.269-273. For an online version of this paper, see http://www.future-fab.com/documents.asp?d_ID=649

[2] M. Soucek, and M. Reddy, Private Communications.

 
 
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