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TEM-based techniques for barrier/seed step coverage analysis in via structures are reviewed. This challenging analytical task requires a dedicated sample preparation. The FIB technique makes it possible to prepare via cross-sections with high accuracy in a reasonable timeframe. The potential and the limits of brightfield and Z contrast imaging as well as of analytical TEM are discussed. The three-dimensional reconstruction of the object using electron tomography and the HAADF imaging of “inner surfaces” are new approaches to characterize the thickness and the uniformity of the barrier and sometimes of the seed layer at the most critical structures, the sidewalls of the vias.
In order to reduce the signal delay of integrated circuits, further shrinking of transistor and interconnect structures as well as the introduction of new materials and processes are required. For this reason, on-chip interconnect fabrication has proceeded from traditional aluminum interconnects and metal etch patterning to the dual in-laid copper technology. Additionally, low dielectric constant materials will replace the silicon dioxide that isolates the copper structures electrically. Figure 1 shows a SEM cross-section through a leading-edge microprocessor (AMD’s eighth generation microprocessor, codenamed Hammer, in 130 nm CMOS technology with 9 metallization layers).
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