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For leading-edge microelectronic products
like microprocessors, each new technology
node that comes along with
smaller dimensions of on-chip interconnects,
advanced backend-of-line (BEoL)
manufacturing process steps and/or
changed combinations of thin film materials
is leading to new reliability challenges:
different microstructure of the
metal interconnects, other types of interfaces
and as yet unknown degradation
phenomena. Electromigration, stressinduced
phenomena and – in case of lowk
materials – mechanical weakness are
reliability concerns for inlaid copper
interconnects.[1,2] Electromigrationinduced
degradation processes in interconnects
are one of the key factors limiting
the reliability of microelectronic products.
With the ongoing scaling-down of
interconnect structures and with the
introduction of new processes and materials,
the understanding and control of
electromigration becomes more and
more important. Although a lot of theoretical
and experimental work has been
done on electromigration of inlaid copper
interconnects, it is still not fully understood
how the interconnect degradation
takes place. Therefore, in addition to statistically
relevant standard reliability
tests, the study of degradation mechanisms
for a limited number of representative
samples is needed to understand
weaknesses in the interconnect technology.
Currently, the integration of low-k
dielectric materials for insulating thin
films that are needed to lower power consumption
and to minimize cross-talk
between on-chip metal interconnects in
leading-edge microelectronic products
results in a challenging task.[3]
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