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Strain engineering has become an
important tool to allow the semiconductor
industry to meet roadmap requirements
for device performance in the face of limits
to device scaling. Strain is used to affect
the electronic band structure to improve
carrier mobility in the channel region of
MOSFET devices. The development of
strain-engineered devices requires the
ability to measure local strains in the critical
channel region of fully processed
devices. Currently, only transmission electron
microscopy (TEM) has proven capable
of measuring such buried strains at the
required spatial resolutions. This article
will review and assess several TEM methods
of local strain measurement. Strain engineering to enhance channelregion
carrier mobility has become an
important tool being developed to achieve
International Technology Roadmap for
Semiconductors (ITRS) requirements for
device performance (ITRS, 2004). Strain is
the distortion resulting from stress.
Distortion of crystalline silicon affects the
electronic band structure, allowing
improvements in carrier mobility (compressive
strain has been used to improve
hole mobility and tensile strain to improve
electron mobility). Several processing
schemes are being used to engineer strain
into the channel region of MOSFET
devices including global methods such as
epitaxial growth of silicon on SiGe
(Numata, 2004) and local methods such as
SiGe source-drain stressors and stressimparting
silicon-nitride overlay films
(Gostkowski, 2005). The local strain in the
channel region of a fully processed device
also depends on subsequent processing
steps such as deposition of additional
material layers, formation of device and
interconnect structures, and thermal
cycling. Thus, device process development
and control require the ability to
measure local strains buried in the channel
region beneath fully processed
devices. Strained silicon technology has
been reviewed by Lee, et al. (Lee, 2005).
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