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How to Survive the Scaling and 450 mm Transition Challenge
(4/25/2013) Future Fab Intl. Issue 45
By Luc Van den hove, imec
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For the past five years, mobile communication and mobile computing have been the main drivers for the IC industry and for the need to scale down transistors. This trend will continue. High-value connectivity will be in the background of everyday lives, connecting people to people and people to their environments.

How to Survive the Scaling and 450 mm Transition Challenge

Luc Van den hove

For the past five years, mobile communication and mobile computing have been the main drivers for the IC industry and for the need to scale down transistors. This trend will continue. High–value connectivity will be in the background of everyday lives, connecting people to people and people to their environments.

Tremendous Opportunities

More new opportunities are on the horizon. Chips will be integrated to enable new diagnostic devices for improved, faster and point–of–care diagnostics. These tremendous opportunities to develop a personal health management system, together with the ever–continuing demand for increased connectivity, will drive the IC industry in the coming years.

Moore's Law has made today's applications possible through a continuous cost reduction of transistors, enabling more system complexity, functionality and performance. Scaling will continue to be important for this purpose, but we are facing times in which scaling will no longer automatically be translated into cost reduction. Unprecedented opportunities and challenges will shape the IC landscape in the coming years.

The complexity of scaling

Device scaling from the 45 nm technology node to the sub–10 nm node has to deal with many different device architectures and material systems. FinFETs and nanowire–based tunnel FETs are being developed in R&D centers, with metal gates, high–k materials, high–mobility channels and carbon nanotubes. With this myriad of scaling routes, scaling is becoming more and more complex. Furthermore, to achieve performance gain at the system level, 3D technology is needed to stack memory on top of logic, analog on top of digital, etc.

Scaling also requires dedicated lithography solutions. With the delay of EUV lithography, there is a risk that the roadmap is slowing down. Since no EUV is available today, techniques like double and triple patterning must be used. However, this leads to a tremendous rise in cost. Key for the coming years will be to get EUV ready because this is the only way to get the cost down for aggressively scaled pitches such as the 14 nm node.

Figure 1. Lab–on–a–chip prototype device for improved, faster and point–of–care diagnostics.

A Cost–Effective 450 mm Wafer Transition

EUV lithography will be key to enable cost–effective scaling. But transitioning toward a larger wafer size can also contribute to staying on the cost curve related to Moore's Law. Going from 300 mm to 450 mm wafer sizes could reduce costs by 30% because of the production efficiencies it would bring. However, a cost reduction with the 450 mm transition is not a given. Major innovations will be needed.

Figure 2. A 450 mm wafer.

First of all, we must consider the wafer–based processes like deposition, etch and cleaning. For 450 mm, new bodies have to be developed, wafer handling has to be innovated, and the process has to be optimized. In this case, we can achieve an efficiency benefit of a factor of 2.25.

The situation is very different, however, for die–based processes such as implantation, inspection and lithography. Here, in terms of cost reduction, you don't gain anything by going to a larger wafer size. Again, innovations are needed for body development, wafer handling and process optimization. The throughput will stay the same while using a more expensive tool.

For lithography, for example, there are many challenges when transitioning to 450 mm. A bigger wafer stage is needed–some 3–4x heavier than for 300 mm wafers. This implies that when using the same stage speed, the acceleration forces will be much higher. As a consequence, the acceleration must be reduced to achieve the same overlay specs. To maintain the same throughput, major innovations will be needed.

Figure 3. The imec campus with a 200 mm, 300 mm and soon a 450 mm R&D facility.

An Open–Innovation Campus

Indeed, major innovations will be needed in the domain of device scaling, lithography and 450 mm tool and process development. Obviously, the required R&D budget to tackle these challenges will increase–at a higher rate than the available R&D budget. We will see a significant consolidation in the IC industry, at the supplier side as well as on the IC manufacturing side. With fewer players in the game, it will be important to organize R&D in the most efficient way. Collaboration in an open–innovation mode is definitely the best way to address both the increasing R&D costs and the enormous technological challenges.

This is where imec wants to make a contribution. With its large expertise in setting up open–innovation programs around the most critical issues in scaling, imec is ready to take on this challenge too. The open innovation initiative has succeeded by bringing together the entire ecosystem–the entire supply chain, and the entire innovation chain. The same kind of initiative will be needed to successfully make the transition toward smaller transistors and bigger wafers.

The first phase of transitioning to bigger wafer sizes mainly deals with equipment development and early tool testing. In this stage, the equipment suppliers will have to take the lead, and in this context the Global 450 Consortium (G450C) is very important. Meanwhile, imec will also set up a 450 mm R&D facility and do some initial 450 mm tool testing in its cleanroom extension next to its 300 mm R&D facility, which was built three years ago and is fully compatible with 450 mm wafers.

By the end of 2015, imec's new 450 mm cleanroom will be ready for tool installation. In this full 450 mm process R&D facility, imec and its R&D partners will focus on materials, process and device development, which has always been the strength of imec. In this environment, we will continue to develop a strong value proposition to both the supplier community and the IC manufacturers. Also, we will be developing a platform where fabless and fablite companies can test out new technology options for the sub–10 nm node.

We are convinced that the only way to tackle the enormous challenges lying ahead of us is through very extensive collaboration. In this way, we will reach the innovation level that we need to make these phenomenal transitions.

About the Author

Luc Van den hove

Luc Van den hove received his Ph.D. in electrical engineering from the University of Leuven in Belgium. He joined imec in 1984, and in 1988 became manager of imec's micro–patterning group. In January 2007, he was appointed as imec's executive vice president and chief operating officer (COO), and in 2009, he became CEO. He has authored or co–authored more than 100 publications and conference contributions. n


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