Editorial Panel

We want Future Fab to be the best, so we have gone out of our way to assemble an editorial panel that we feel is the best. World-ranking technologists and consultants, these are people who have earned the respect shown to them by the industry. We thank all of them for their unfailing good humor, advice and assistance.

Click on a panel member below for a full biography.

• Rohan Akolkar Senior Process Engineer, Components Research; Intel Corporation
• Pushkar P. Apte President of Pravishyati Inc.
• Sitaram R. Arkalgud Vice President of 3D Products, Invensas
• 'Surya' Suryanarayana Shivakumar Bhattacharya Director, Industry Development; IME
• Christian Boit Head of Semiconductor Devices at Berlin University of Technology, Germany
• Christo Bojkov Senior Package Development Engineer, TriQuint Semiconductor
• Michel Brillouët Senior Adviser, CEA-LETI
• Stephen J. Buffat Staff Research Scientist, Lockheed Martin NanoSystems
• Jon Candelaria Director, Interconnect and Packaging Sciences; SRC
• William T. Chen Senior Technical Advisor, ASE (U.S.) Inc.
• Luigi Colombo TI Fellow
• Gilbert J. Declerck Executive Officer imec and Member of the Board of Directors imec International
• Alain Charles Diebold Empire Innovation Professor of Nanoscale Science, Executive Director, Center for Nanoscale Metrology; College of Nanoscale Science and Engineering, University at Albany; AVS Fellow; Senior Member of IEEE
• Daniel C. Edelstein IBM Fellow; Manager, BEOL Technology Strategy; T.J. Watson Research Center
• Paul A. Farrar, Jr General Manager, Global 450mm Consortium (G450C), CNSE Vice President for Manufacturing Innovation
  
• Giuseppe Fazio Advanced Process and Equipment Control Sr. Engineer, Micron Semiconductors Italy
• Paolo A. Gargini IEEE Fellow and IEC Fellow
• Janice M. Golda Director, Lithography Capital Equipment Development; Intel
• Steve Greathouse Global Process Owner for Microelectronics, Plexus Corporation
• Daniel J.C. Herr Professor & Nanoscience Department Chair, University of North Carolina at Greensboro
• Alain E. Kaloyeros Senior Vice President and CEO; Professor of Nanoscience College of Nanoscale Science and Engineering, University at Albany
• Lode Lauwers Director, Strategic Program Partnerships for Silicon Process and Device Technology, imec
• Yannick Le Tiec Technical Expert, CEA-Leti MINATEC
• Davide A. Lodi Baseline Defectivity & Metrology Manager, Micron Semiconductors Italy
• Didier Louis Corporate and International Communication Manager, CEA-Leti
• Liam Madden Corporate Vice President, FPGA Development & Silicon Technology
• Raj N. Master General Manager, IC Packaging, Quality and Reliability; Microsoft Corporate Fellow; AMD
• Peter Rabkin Director of Device and Process Technology, Sandisk Corp.
• Peter Ramm Head of Device and 3D Integration Department, Fraunhofer EMFT; Munich
• Shishpal Rawat Chair, Accellera Systems Initiative; Director, Intel Corp.
• Klaus-Dieter Rinnen Director/Chief Analyst, Dataquest
  
• Warren Savage Chief Executive Officer, IPextreme
• John Schmitz SVP & General Manager, Intellectual Property and Licensing; NXP Semiconductors
• Steven Schulz President and Chief Executive Officer Silicon Integration Initiative, Inc.
  
• David G. Seiler Chief, Semiconductor and Dimensional Metrology Division; NIST
  
• Thomas Sonderman Vice President, Manufacturing Systems Technology; GLOBALFOUNDRIES
• Alan Weber President, Alan Weber and Associates
• Yayi Wei Principal Member of Technical Staff; GLOBALFOUNDRIES
• Jiang Yan Professor, Institute of Microelectronics, Chinese Academy of Sciences
• Ehrenfried Zschech Division Director for Nanoanalysis and Testing, Fraunhofer Institute for Nondestructive Testing; Dresden, Germany

Rohan Akolkar
Senior Process Engineer, Components Research; Intel Corporation

Dr. Akolkar is a senior process engineer in Components Research at Intel Corporation, Hillsboro, Ore. His research interests include novel materials and deposition strategies for BEOL interconnect fabrication. Dr. Akolkar received the Norman Hackerman Prize of the Electrochemical Society in 2004, and numerous Intel Logic Technology Development awards. He has authored more than 40 technical papers, invited talks, and U.S. patents in the area of electrodeposition. Dr. Akolkar is a member of the Electrochemical Society.

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Pushkar P. Apte
President of Pravishyati Inc.

Dr. Pushkar P. Apte is currently president of Pravishyati Inc., a strategy consulting firm focused on the high-tech industry. He received his master’s and Ph.D. degrees from Stanford University in materials science and electrical engineering, and his bachelor’s degree in ceramic engineering from the Indian Institute of Technology, Varanasi, India. Dr. Apte has worked with Texas Instruments Inc. on cutting-edge research and technology development; with McKinsey & Co. as their global semiconductor business expert; and with the Semiconductor Industry Association as their vice president of Technology Programs. He has over 50 publications and presentations in prestigious international journals, conferences and institutions, including invited papers. Dr. Apte has received the Norman Hackerman Young Author Award from the Electrochemical Society for Best Paper in the Journal of the Electrochemical Society, and the Graduate Student Award from the Materials Research Society for Outstanding Research Performance. He holds two U.S. patents..

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Sitaram R. Arkalgud
Vice President of 3D Products, Invensas

Sitaram Arkalgud is vice president–3D products at Invensas, where he recently joined after serving as director of SEMATECH's Interconnect Division. He has more than 20 years of R&D and manufacturing experience with the chip industry. He has a Ph.D. and a master's degree in materials engineering from Rensselaer Polytechnic Institute, and a B.S. in metallurgical engineering from Karnataka Regional Engineering College, Surathkal, India.

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'Surya' Suryanarayana Shivakumar Bhattacharya
Director, Industry Development; IME

Christian Boit
Head of Semiconductor Devices at Berlin University of Technology, Germany

Christian Boit is head of the semiconductor device department of the Berlin University of Technology, an institution for research and development in the areas of device simulation, technology, characterization, and reliability, with special focus on device localization and repair from the backside of the die. He received a diploma in physics and a Ph.D. in electrical engineering on power devices, then joined Siemens AG’s Research Laboratories for Semiconductor Electronics in Munich and has been a pioneer on photo-emission. He was a delegate to the the joint IBM-Siemens 64M DRAM Development Team in East Fishkill, N.Y., and until 2002 was director of failure analysis for Infineon Technologies AG. He has contributed on various fields in technology, device characterization, and analysis, with photoemission as a center of gravity. On this topic he is a lecturer on ISTFA’s Seminar and in 1993 received the German VDE-itg Award. He is member at large of the EDFAS board of directors and a member of VDE (German Society of Electrical Engineering). He serves on the ISTFA organizing committee (2002 general chairman), on committees of ESREF and IPFA, and is chairing the EDFAS Publication Committee.

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Christo Bojkov
Senior Package Development Engineer, TriQuint Semiconductor

Dr. Christo Bojkov is a senior package development engineer with TriQuint Semiconductor. He has over 20 years of TR&D experience in FEOL and BEOL with number of semiconductor companies: Wacker Siltronic, Texas Instruments, Dallas Semiconductor and Freescale. Christo has published more than 30 publications and has 15 patents in Europe and the U.S. Since receiving his doctorate in chemical engineering, he has worked and taught in academia for over 10 years in physical chemistry and surface science, with the universities of: Paris (France), Rome (Italy), Max-Planck Institute (Germany) and Texas A&M. Currently Christo serves on the technical committee of EMC^3D - Equipment and Materials Consortium for 3D-TSV and IC Interconnect.

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Michel Brillouët
Senior Adviser, CEA-LETI

Michel Brillouët is a senior adviser with CEA-LETI. He joined CEA-LETI in 1999, where he managed the silicon R&D. Prior to joining CEA-LETI, he worked for 23 years in the Centre National des Télécommunications (France Telecom R&D Center), where he held different positions in microelectronics research. He graduated from École Polytechnique.

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Stephen J. Buffat
Staff Research Scientist, Lockheed Martin NanoSystems

Stephen Buffat is a staff research scientist and operations manager of the Jordan Valley Innovation Center for Lockheed Martin NanoSystems in Springfield, Mo. He is an adjunct faculty member at the Center of Applied Science and Engineering/JVIC Center at Missouri State University. Stephen is responsible for the startup and operation of Lockheed Martin’s nanotechnology facility and operation in Springfield, Mo. He has authored or co-authored numerous articles on photolithography, etch and 300 mm surface preparation process technologies.

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Jon Candelaria
Director, Interconnect and Packaging Sciences; SRC

Jon Candelaria is the director of the Interconnect and Packaging Sciences area for SRC. He has over 34 years’ experience in the electronics industry in a wide variety of engineering and managerial roles. Prior to joining SRC, Jon was a Distinguished Member of the technical staff at Motorola’s Applied Research & Technology Center. He received his BSEE and MSEE from the University of New Mexico.

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William T. Chen
Senior Technical Advisor, ASE (U.S.) Inc.

William Chen (Bill) is senior technical advisor at ASE (U.S.) Inc. He is the co-chair of the ITRS Assembly and Packaging International Technical Working Group. Bill has published extensively in the fields of microelectronics packaging and mechanics of materials. He has been elected a Fellow of IEEE and a Fellow of ASME. Bill received his B.Sc. at University of London, M Sc at Brown University and Ph.D. at Cornell University.

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Luigi Colombo
TI Fellow

Dr. Luigi Colombo is a TI Fellow working on the Nanoelectronic Research Initiative (NRI). He has led the development of high-k dielectrics for CMOS devices, and HgCdTe for infrared detectors. He is author and co-author of over 130 publications, three book chapters, and holds over 60 U.S. patents. Dr. Colombo received his Ph.D. in materials science from the University of Rochester.

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Gilbert J. Declerck
Executive Officer imec and Member of the Board of Directors imec International

Gilbert J. Declerck received his Ph.D. in electrical engineering from the University of Leuven in 1972. From 1973 to 1974, he worked in the IC laboratories of Stanford University. Dr. Declerck then moved to Leuven University (Belgium) in 1974, where he became professor in 1983. In 1984, he joined imec (Leuven, Belgium), as vice president of the Advanced Semiconductor Processing Division. Dr. Declerck authored and co-authored over 200 papers and conference contributions. In 1993, he was elected fellow of the Institute of Electrical and Electronics Engineers (IEEE), awarding his leadership and contributions to metal-oxide semiconductor device physics, charge-coupled device technology and very-large-scale integration processing techniques. In 1998, Dr. Declerck was appointed chief operating officer of imec. From June 1999 through June 30, 2009, he was imec's president and CEO. Since July 1, 2009, Dr. Declerck has been executive officer imec and a member of the board of directors of imec International. He is chairman of the scientific committee of MEDEA+ and a member of the MEDEA+ board. Dr. Declerck is a member of several advisory boards of scientific institutes and companies.

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Alain Charles Diebold
Empire Innovation Professor of Nanoscale Science, Executive Director, Center for Nanoscale Metrology; College of Nanoscale Science and Engineering, University at Albany; AVS Fellow; Senior Member of IEEE

Alain recently became a professor at the College of Nanoscale Science and Engineering at the University at Albany. His research will focus on the impact of nanoscale dimensions on the physical properties of materials; he also continues to work in the area of nanoelectronics metrology. He is a member of the International Metrology Technical Working Group, founder and co-chair of the U.S. Metrology Technical Working Group for the 2007 International Technology Roadmap for Semiconductors, and chair of the Manufacturing Science and Technology Group of the American Vacuum Society. He was a SEMATECH Senior Fellow, with the main focus of his activities involving metrology industry coordination. He has edited the Handbook of Silicon Semiconductor Metrology, published in June 2001; is a Panel Member for the Metrology section of Future Fab International; and, he has co-edited three books that are conference proceedings from Characterization and Metrology for ULSI Technology and its predecessor conference. He also worked at Allied Signal in the areas of molecular beam epitaxy of III-V compounds and materials characterization of a broad range of semiconductor and amorphous metal products.

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Daniel C. Edelstein
IBM Fellow; Manager, BEOL Technology Strategy; T.J. Watson Research Center

Dr. Edelstein is an IBM Fellow, and Manager of BEOL Technology Strategy at the T. J. Watson Research Center. He played a leadership role in IBM's industry-first "Cu Chip" technology in 1997, in the introduction to manufacturing of Cu/Low-k insulation in 2004, and most recently in the airgap wiring announcement. Dr. Edelstein received his B.S., M.S., and Ph.D. degrees in Applied Physics from Cornell University.

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Paul A. Farrar, Jr
General Manager, Global 450mm Consortium (G450C), CNSE Vice President for Manufacturing Innovation

Paul Farrar is General Manager of the Global 450mm Consortium (G450C) and oversees the coordination, administration and management of G450C’s strategic, operational and financial missions, including external collaborations with international partner companies, program staffing, and interactions with the G450C Management Council. In addition, he serves as CNSE Vice President for Manufacturing Innovation, where he is responsible for the expansion of CNSE’s intellectual know-how and state-of-the-art programs to convert long-term prospective innovations into business opportunities and economic development programs across New York. Farrar joined CNSE with more than 32 years of experience in the semiconductor industry. Farrar received a bachelor’s degree and a master’s degree in Materials Engineering from Rensselaer Polytechnic Institute.

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Giuseppe Fazio
Advanced Process and Equipment Control Sr. Engineer, Micron Semiconductors Italy

With a laurea degree in applied physics from Milan University, Giuseppe has working experience in several sectors, from research to industry, and vast experience in industrial and scientific instrumentation, as well as in the sector of components for industrial automation. After many years with ST Microelectronics, he is now in the R&D division of Micron Semiconductors Italy. Giuseppe has authored and co-authored numerous articles, is an avid contributor at conferences and holds several patents in the semiconductor field.

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Paolo A. Gargini
IEEE Fellow and IEC Fellow

Paolo Gargini (IEEE Fellow and IEC Fellow) recently joined forces with the electrical engineering staff of Stanford University after 34 years working at Intel Corp. During his tenure at Intel, he was director of technology strategy in Santa Clara, Calif., and was responsible for worldwide research activities conducted by universities and consortia for the Technology and Manufacturing Group. Gargini was born in Florence, Italy, and received a doctorate in electrical engineering in 1970 and a doctorate in physics in 1975 from the Università di Bologna, Italy, both with full honors and marks. He has done research at LAMEL in Bologna, Stanford Electronics Laboratory, and Fairchild Camera and Instrument Research and Development in Palo Alto, Calif., from 1970 to 1977. After joining Intel in 1978, he conducted studies on process reliability; he was responsible for developing the building blocks of HMOS III and CHMOS III technologies used in the 1980s for the 80286 and the 80386 processors. In 1985 he headed the first submicron process development team at Intel. In 1995, he was elevated to Intel Fellow. Gargini has been the chairman of the Executive Steering Council (ESC) of I300I and, subsequently, of International Sematech from 1996 to 2000. He was then a member of the SEMATECH Board until 2012. Since 1998, Gargini has been chairman of the International Technology Roadmap for Semiconductors (ITRS). He has been a member of various technical committees and technical advisory boards for organizations such as the Semiconductor Research Corp. (SRC), and the Technology Strategic Council (TSC) of the SIA in the United States, IMEC in Europe, and ASET and MIRAI in Japan. He also heads the International EUV Initiative (IEUVI), which fosters cooperation and coordination among the largest EUV consortia in the world. Gargini chairs the International Consortia Cooperation Initiative (ICCI), which fosters exchange of information among a selected group of leading consortia and institutes in the world. He initiated and became the first chairman of the Governing Council of the Nanoelectronics Research Initiative (NRI), funded by SIA and aimed at supporting and focusing research in universities toward subsequent commercialization of nanoelectronics. In 2003, Gargini was included by EE Times in a very select group of Influencers of the semiconductor industry, and was inducted into the VLSI Research Hall of Fame in 2009.

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Janice M. Golda
Director, Lithography Capital Equipment Development; Intel

Janice Golda manages an organization responsible for creating strategies and working with Intel's lithography, mask and metrology suppliers and subsuppliers to deliver equipment meeting Intel's roadmap technology, capacity and cost requirements. She is a member of the Berkeley CXRO Advisory committee, is Chairman of the Board for the EUV LLC and holds one U.S. patent. She earned her B.S. in electrical engineering from Cornell University.

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Steve Greathouse
Global Process Owner for Microelectronics, Plexus Corporation

Steve Greathouse is the Global Microelectronics Process Technology manager at Plexus Corporation, in Nampa, Idaho, responsible for the development and deployment of microelectronic devices worldwide for Plexus. He has published many articles on technical topics related to semiconductor packaging, failure analysis and lead-free packaging. Steve has a B.S. in electronic physics from Weber State University with advanced studies in material science and computer science.

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Daniel J.C. Herr
Professor & Nanoscience Department Chair, University of North Carolina at Greensboro

Dr. Herr is a pioneer in collaborative nanotechnology research. He is professor and chair of the Nanoscience Department at the new Joint School for Nanoscience and Nanoengineering in Greensboro, North Carolina. Until recently, Dr. Herr served as the director of Semiconductor Research Corporation’s Nanomanufacturing Sciences area, leading an international team that provides vision, guidance and leveraged support for a number of the top interdisciplinary, nanoelectronics-related university research programs. He also serves as adjunct associate professor in materials science and engineering at North Carolina State University, where he co-teaches a graduate-level course on the materials science of nanoelectronics. Dr. Herr founded a quality engineering startup that enabled rapid and robust custom product material and process design. His suite of applied optimization tools is significantly more robust than Taguchi’s methodology. More recently, he was elected to serve as the AAAS Industrial Science and Technology section’s Member-at-Large, and Fellow of the International Society for Optical Engineering for the design, development and commercialization of two early families of chemically amplified resists. Dr. Herr is the inventor of several foundational patents and disclosures on defect-tolerant patterning, controlled nanotube synthesis and placement, deterministic semiconductor doping and ultimate CMOS devices. As founding co-chair of the International Technology Working Group on Emerging Research Materials, he provides ongoing technical leadership for the ITRS community. Dr. Herr also serves as senior editor for IEEE Transactions in Nanotechnology, as coordinating editor for the Journal of Nanoparticle Research, as reviewer for the Journal of Vacuum Science and Technology and as co-chair of several international technical conferences. He was a contributing team member when SRC was awarded the 2005 National Medal of Technology. Dr. Herr received his B.A. with honors in chemistry from Wesleyan University in 1976 and his Ph.D. from the University of California at Santa Cruz in 1984.

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Alain E. Kaloyeros
Senior Vice President and CEO; Professor of Nanoscience College of Nanoscale Science and Engineering, University at Albany

Alain E. Kaloyeros, Ph.D., is professor, SVP and CEO of the College of Nanoscale Science and Engineering (CNSE) of the University at Albany-SUNY. He also serves as vice president and special advisor to the president for Universitywide Economic Innovation and Outreach. Dr. Kaloyeros received his Ph.D. in experimental condensed matter physics from the University of Illinois, Urbana-Champaign in 1987. He has authored and co-authored over 150 articles and contributed to eight books on topics pertaining to the science and technology of nanoelectronics and nano-optoelectronics ultrathin film materials, atomic layer vapor phase deposition processes, and nanoscale X-ray, electron, and photon-based characterization and metrology. Dr. Kaloyeros holds 13 U.S. patents. He is a past recipient of the NSF Presidential Young Investigator Award, the NSF Research Initiation Award, the Albany Foundation 1995 Academic Laureate Award, the 1997 Center for Economic Growth Enterprise Award, the 1999 Citizen of the University Award, the 2002 Outstanding Inventor Award of the SUNY RF, the R&D 100 Award for one of the Most Technologically Significant Inventions of 2001, the 2003 Excellence in the Pursuit of Knowledge Award of the SUNY Research Foundation, and the 2004 Research Foundation Partnership in Leadership Award. Dr. Kaloyeros was also the recipient of the 2005 Tech Valley Summit Mentorship, Innovation, Knowledge, and Entrepreneurship Award on behalf of CNSE's executive leadership team. He was selected for the 2003, 2005, 2007 and 2008 "Tech Valley's Hot 10," an annual list of the "top 10 movers and shakers" in New York's Capital Region compiled by the Albany-Colonie Chamber of Commerce and the Capital Region media. Dr. Kaloyeros is listed in the Marquis Who's Who in Science and Engineering, 2006-present; the AcademicKeys Who's Who in Higher Education Administration, 2005-present; and the AcademicKeys Who's Who in Sciences Higher Education, 2004-present. Dr. Kaloyeros has been actively involved in the development and implementation of New York's high tech strategy to become a global leader in the nanotechnology driven economy of the 21st century.

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Lode Lauwers
Director, Strategic Program Partnerships for Silicon Process and Device Technology, imec

Lode Lauwers has an M.S. in Electronics Engineering and a Ph.D. in Applied Sciences. He joined imec in 1985 as a researcher. In 1992, he became scientific advisor at IWT, and in 2000 general manager at Easics NV. He is currently Director Strategic Program Partnerships for Silicon Process and Device Technology at imec, managing imec's core partner research program on sub-32nm CMOS technologies.

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Yannick Le Tiec
Technical Expert, CEA-Leti MINATEC

Yannick Le Tiec is a technical expert at CEA-Leti. He joined CEA-Leti in 1995 and received his Ph.D. in materials science and engineering from the Polytechnic Institute, Grenoble, France, and his M.S. in chemistry from the National School of Chemistry, Montpellier, France. He worked for four years in the field as an application engineer for Metron Technology, working with FSI cleaning equipments. Hired by CEA-Leti in 2002, Le Tiec held different technical positions from the advanced 300 mm SOI CMOS pilot line to different assignments within SOITEC for advanced wafer development and later within INES to optimize solar cell ramp-up and yield. He is now a CEA-Leti assignee at IBM, Albany (NY) to develop the advanced 22 nm CMOS node and the FDSOI technology. Le Tiec has been part of the ITRS Front End technical working group at ITRS since 2008.

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Davide A. Lodi
Baseline Defectivity & Metrology Manager, Micron Semiconductors Italy

Davide A. Lodi is the baseline defectivity and metrology engineering manager at Micron F14, in Agrate, Italy. After graduating in physics from the University of Milan, he started working in 1997 for STMicroelectronics as a process engineer. After becoming the manager of Wet Processes and Metrology Engineering at the NVM R&D site in Agrate, he moved to Numonyx, which was acquired by Micron in 2010.

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Didier Louis
Corporate and International Communication Manager, CEA-Leti

After working for three years at Thomson Electronic Tubes Division, where the research emphasis was on improvement and characterization of medical electronic tubes, Louis joined CEA-Leti (France) in 1985, where he received a Ph.D. in metallurgy/electrochemistry from the University of Grenoble. Since joining CEA-Leti, Louis has held different positions in microelectronics research in process development and team management. In 2000, he was manager of the Etching and Stripping R&D laboratory. From July to December 2003, he was the Nanotec300 Joint development Program Manager. From 2004 to 2007, he was the Deputy Manager of the Back End of Line laboratory. From 2008 to 2010, he was the deputy manager of the Materials and Modules laboratory and public relation manager of the Nanoelectronic division. In 2010, he joined the directorate staff of Leti as corporate and international communication manager. He has written more than 30 papers related to etching and stripping processing and has co-authored more than 60 scientific papers and eight patents. He has been involved in several European projects as work package leader. He plays an active role in the organization of several international conferences, such as IITC (International Interconnect Technology Conference), MNE (Micro and Nano Engineering), PESM (Plasma Etch and Strip in Microelectronics) and AVS-ICMI (over three years). He is a member of the ITRS committee of the Interconnect group. He is a member of SEMI STC Group. Louis graduated from Electro-chemical en Material Engineering Scholl in 1988.

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Raj N. Master
General Manager, IC Packaging, Quality and Reliability; Microsoft Corporate Fellow; AMD

Master is the general manager of IC Packaging, Quality and Reliability for all hardware products at Microsoft. Previously, he managed the advanced packaging group involved in developing strategic enabling technologies and was also manager of the lead-free program of AMD. Master joined AMD after spending 21 years at IBM, where he was a senior technical staff member. He has 47 U.S. patents issued to him and has published more than 70 technical papers.

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Peter Rabkin
Director of Device and Process Technology, Sandisk Corp.

Dr. Peter Rabkin is currently director of Device and Process Technology at Sandisk Corp. focusing on development of novel 3D memory technologies and products. Before that, he served as program director for Advanced Technology Development at Xilinx, Inc., responsible for process-to-design integration and DFM. Prior to Xilinx, Dr. Rabkin was director of Advanced Technologies at PDF Solutions, Inc., and held a number of other senior managerial and technical positions, including roles at Hynix Semiconductor, Hyundai Electronics and Silvaco International. With over two decades in the semiconductor industry, he was involved in the development and transfer to volume production of a wide variety of semiconductor processes, devices and products, spanning from cutting-edge CMOS, to advanced memories, to devices of power electronics and high-performance heterojunction applications. Dr. Rabkin is currently an elected member of the IEEE SCV Electron Device Society Committee, and has been an editorial panel member and contributing editor of Future Fab International since 2005. He has authored and co-authored over 80 publications, and has been an invited presenter and panel member at numerous reputable technical and business forums. He also holds 13 U.S. patents. Dr. Rabkin holds a master's degree in physics from Tartu University and a Ph.D. in physics of semiconductors from the St. Petersburg Institute of Physics and Technology.

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Peter Ramm
Head of Device and 3D Integration Department, Fraunhofer EMFT; Munich

Peter Ramm is head of the department Device and 3D Integration of Fraunhofer EMFT in Munich, Germany, where he is responsible for process integration of innovative devices and heterogeneous systems with a specific focus on 3D integration technologies. He received the physics and Dr. rer. nat. degrees from the University of Regensburg and subsequently worked for Siemens in the DRAM facility, where he was responsible for the process integration. In 1988, Dr. Ramm joined Fraunhofer IFT in Munich, focusing for two decades on 3D integration technologies. He is author or co-author of more than 100 publications, including 23 patents, and co-editor of Wiley's "Handbook of 3D Integration." Dr. Ramm received the "Ashman Award 2009" from the International Electronics Packaging Society (IMAPS) for "For Pioneering Work on 3D IC Stacking and Integration."

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Shishpal Rawat
Chair, Accellera Systems Initiative; Director, Intel Corp.

Shishpal Rawat is chair of Accellera, an EDA industry standards organization, and director of Business-Enabling Programs with the Design Technology Solutions group at Intel. He oversees Intel's research investments in academia, collaboration with industry standards bodies and collaborates with Intel Capital on EDA equity investments. Shishpal has been at Intel for 22 years and has held a variety of design and CAD management positions. He holds M.S. and Ph.D. degrees in computer science from Pennsylvania State University, University Park, and a B. Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India.

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Klaus-Dieter Rinnen
Director/Chief Analyst, Dataquest

Klaus-Dieter Rinnen is director for Dataquest’s semiconductor and electronics manufacturing group, which covers trends and competitive positioning in semiconductor capital equipment, materials, contract manufacturing (foundry and SATS), and electronics manufacturing services. Before joining Dataquest, he was at Applied Materials and AT&T Bell Laboratories. He earned a diploma degree in physics with minors in physical chemistry and mechanical engineering in Germany and a Ph.D. in applied physics from Stanford University.

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Warren Savage
Chief Executive Officer, IPextreme

Warren Savage has spent his entire career in Silicon Valley, working with leading companies including Fairchild Semiconductor, Tandem Computers and Synopsys, where he focused on the problem of building a global scalable semiconductor IP business. In 2004, he founded, and still leads IPextreme in the mission of unlocking and monetizing captive intellectual property held within semiconductor companies and making it available to customers all over the world. He holds a B.S. in computer engineering from Santa Clara University and an MBA from Pepperdine University.

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John Schmitz
SVP & General Manager, Intellectual Property and Licensing; NXP Semiconductors

John Schmitz is VP and general manager of Intellectual Property and Licensing, overseeing all IP-rights-related matters for NXP Semiconductors. From September 2005 to April 2011, he was a VP of process technology research, overseeing research activities in IC process and device technologies. Prior to that, Schmitz served as VP and COO for manufacturing technology of SEMATECH from April 2002 to December 2005. There he launched the Advanced Technology Development Facility (ADTF) for-profit subsidiary as well as the International SEMATECH Manufacturing Initiative (ISMI) subsidiary. Prior to coming to SEMATECH, Schmitz served as VP and general manager of MOS4YOU in the Netherlands, Philips Semiconductors' advanced development and manufacturing unit for embedded nonvolatile memories. He joined Philips Research Labs in 1984, where he worked on various interconnect systems for advanced integrated circuits. After that, Schmitz served as a director of process development at Genus Inc. He worked for two years in the joint ST-Philips development center in Crolles, France, in the development and manufacture of planarization techniques and dielectric materials as a group leader. Schmitz holds a master's degree in chemistry from Radboud University of Nijmegen, Netherlands, and a doctorate in physical chemistry from Radboud University Nijmegen. He has authored more than 45 papers in various scientific journals and has written books on IC technology, titled "Chemical Vapor Deposition of Tungsten and Tungsten Silicides for VLSI/ULSI Applications,” and on thermodynamics titled "The Second Law of Life.” Schmitz holds six patents in the areas of PECVD-TiSi2 and CVD-W.

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Steven E. Schulz
President and Chief Executive Officer Silicon Integration Initiative, Inc.

Since 2002, Steve Schulz has served as president and CEO of Si2, the leading worldwide consortium of semiconductor and software companies chartered to develop EDA standards. Steve was previously VP of corporate marketing for BOPS Inc. and was employed by Texas Instruments for 19 years. At TI, Steve was a Senior Member of the Technical Staff and held a wide variety of management and technical positions, including CAD strategy manager and reliability strategy manager. Representing TI, he served as chairman of the Design Sciences Technical Advisory Board for Semiconductor Research Corporation. He has vast experience in standards, having served as president of VHDL International, co-chairman of Accellera, and chairman of the VITAL and SLDL/Rosetta standards initiatives. He has authored more than 150 articles on EDA and IC design methodology, and was a founding editor of Integrated Systems Design magazine. Steve has served on numerous boards, including CADstone Inc., SCDSource.com, ProphICy Semiconductor and CMP Publications. Steve has a Bachelor of Science degree in electrical engineering from the University of Maryland at College Park, and an M.B.A. from the University of Texas at Dallas. He is an active jazz trombone musician in the Austin area.

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David G. Seiler
Chief, Semiconductor Electronics division, Physical Measurement Laboratory; NIST

David G. Seiler is chief of the Semiconductor Electronics division in the Physical Measurement Laboratory at the National Institute of Standards and Technology (NIST). The primary mission of the division is to provide technical leadership in R&D of the semiconductor measurement infrastructure needs essential to the silicon microelectronics industry, advanced semiconductor materials technologies, and advanced electronic devices based on molecular or quantum structures. He received his Ph.D. and M.S. in physics from Purdue University and his B.S. in physics from Case Western Reserve University. In 2000, Dr. Seiler received a Distinguished Alumni Award from Purdue University's School of Science for his contributions and achievements in semiconductors. Over the past 40 years, he has developed an extensive research background in many areas of semiconductor physics. Dr. Seiler’s current focus is on understanding and advancing the metrology and characterization measurements needed by the semiconductor industry. The results of his research have been disseminated in over 200 publications and 100 talks throughout the world. Dr. Seiler currently serves on the IEEE Electron Device Society's Semiconductor Manufacturing Committee and the Governing Council of the Nanoelectronics Research Initiative. He is the co-editor and a co-author of a chapter in vol. 36 of Semiconductors and Semimetals (1992) and is a co-author of the chapter "Optical Properties of Semiconductors" in the McGraw Hill Handbook of Optics (1995, revised in 2009). Additionally, Dr. Seiler is a Fellow of the American Physical Society and a Fellow of the Institute of Electrical and Electronic Engineers (IEEE). Prior to joining NIST in 1988, he served as a solid state physics program director in the Materials Research division at the National Science Foundation and had been a Regents Professor of physics at the University of North Texas.

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Thomas Sonderman
Vice President, Manufacturing Systems Technology; GLOBALFOUNDRIES

Thomas Sonderman is the VP of Manufacturing Systems Technology for GLOBALFOUNDRIES. He obtained a B.S. in chemical engineering from the Missouri University of Science and Technology in 1986 and an M.S. in electrical engineering from National Technological University in 1991. He is the author of 43 patents and has published numerous articles in the area of automated control and manufacturing technology.

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Alan Weber
President, Alan Weber and Associates

Alan Weber is the president of Alan Weber and Associates, a consulting company specializing in semiconductor advanced process control, e-diagnostics, and other related manufacturing systems technologies. Before founding his own company, he was the vice president/general manager of the KLA-Tencor Control Solutions division, acquired from ObjectSpace in March 2000. While at ObjectSpace, he was responsible for all aspects of the company’s semiconductor manufacturing systems business, including development of the APC framework and its eventual commercialization and global marketing/deployment as the Catalyst APC product. Before joining ObjectSpace in early 1997, he spent eight years at SEMATECH and was responsible for advanced manufacturing systems and related standards R&D, including the CIM framework. Before that, he spent 16 years at Texas Instruments managing a variety of technology programs in the semiconductor CAD and industrial automation/control businesses, including a four-year tour of duty in Europe. He holds bachelor’s and master’s degrees in electrical engineering from Rice University.

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Yayi Wei
Principal Member of Technical Staff; GLOBALFOUNDRIES

Dr. Yayi Wei received his master’s degree in engineering from the Electronics Institute, Chinese Academy of Sciences, Beijing, China in 1992 and his doctor degree (Doktor der Naturwissenschaften) from the Max-Planck-Institute for Solid-State Research, Stuttgart, Germany in 1998. As a graduate student in the Max-Planck-Institute for Solid-State Research, Dr. Wei specialized in the electronic transportation of low-dimension structures and micro-fabrications. After receiving his doctorate, Dr. Wei worked in the Oak Ridge National Laboratory (ORNL) on electron-beam lithography and nano-fabrications. In 2001, he joined Infineon Technologies and participated in the process development and material evaluation of advanced lithography in 193 nm, 157 nm, 193 nm immersion and EUV. Dr. Wei joined GLOBALFOUNDRIES in 2009 and served as a senior member of the technical staff, investigating advanced lithography processes and materials. Dr. Wei has numerous publications and holds several patents in the field of lithography.

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Jiang Yan
Professor, Institute of Microelectronics, Chinese Academy of Sciences

Jiang Yan is a professor at the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS), Beijing, China. He received his bachelor's degree from the University of Science and Technology of China, Hefei, China in 1983 and his master's degree from the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China in 1986. Dr. Yan received his Ph.D. in electrical engineering from the University of Texas at Austin, in 1999. He worked for IMECAS from 1986 to 1992. From 1992 to 1995, Dr. Yan was a visiting scholar at the Microelectronics Center of the University of Texas at Austin. He joined Infineon Technologies in 1999. During the 10 years he worked at Infineon, Dr. Yan was involved in the Alliance with IBM, Samsung, GLOBALFOUNDIRES, STMicroelectronics, Toshiba, etc., to develop the CMOS technologies from 0.18 μm to 32 nm nodes. Dr. Yan has more than 20 years of experience in microelectronics. He authored or co-authored more than 40 papers and holds 17 U.S. patents and 10 China patents.

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Ehrenfried Zschech
Division Director for Nanoanalysis and Testing, Fraunhofer Institute for Nondestructive Testing; Dresden, Germany

Ehrenfried Zschech is the deputy director of Nanoanalysis and Testing at Fraunhofer Institute for Nondestructive Testing in Dresden, which he joined in 2009. His responsibilities include nanotesting and nanoanalysis as well as R&D in the field of nanosensors. He received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. Dr. Zschech gathered industry experience during 17 years in several technical and management positions at Airbus and AMD. He has published three books and more than 100 papers in scientific journals in the areas of solid-state physics and materials science. Dr. Zschech is honorary professor for nanomaterials at the Brandenburg University of Technology in Cottbus, Germany. In 2009, he was elected as vice president of the Federation of European Materials Societies (FEMS).

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