- Christian
Boit Head of Semiconductor Devices at Berlin University
of Technology, Germany
- John
Caffall Director of Operations, Submicron Development
Center (SDC); Spansion LLC
- Gilbert
Declerck President and CEO, IMEC
- Alain
Charles Diebold Empire Innovation
Professor of Nanoscale Science
AVS Fellow and Senior Member of IEEE
- Giuseppe
Fazio Advanced Process and Equipment Control Sr. Engineer,
Numonyx
- Daniel
J.C. Herr Director
of Nanomanufacturing Science Research, Semiconductor Research Corporation
- Paolo
A. Gargini Director of Technology Strategy for Intel Corporation
- Janice
M. Golda Director,
Lithography Capital Equipment Development; Intel
- Steve
Greathouse Global Microelectronics Process Technology
Manager, Plexus Corporation
- Davide
A. Lodi Wet Processes & Metrology Engineering
Manager, Numonyx™
- Raj
N. Master Senior AMD Fellow, Chief
Technologist, Advanced Micro Devices
- Peter
Rabkin Director of Device and Process Technology, Sandisk
Corp.
- Peter
Ramm
Head of Dept. Si Technology and VSI, Fraunhofer IZM, Munich
- Ernst
Richter Technology Transfer Manager, Inotera Memories / Qimonda
- Klaus-Dieter
Rinnen
Director/Chief Analyst, Dataquest
- John
Schmitz
Vice President, NXP Semiconductors Research
- Steven
Schulz
President and Chief Executive Officer Silicon Integration Initiative,
Inc.
- Alan
Weber President, Alan Weber and Associates
- Jeff
Wetzel Senior Member, Technical Staff, SVTC, LLC
- Kazuyoshi
"Kazu" Yamada VP, Custom SoC Solutions Strategic Business
Unit, NEC Electronics America, Inc.
- Ehrenfried
Zschech Manager, Center of Complex Analysis, AMD Saxony
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 Christian
Boit
Head of Semiconductor Devices at Berlin University of
Technology, Germany
Christian Boit is
head of the semiconductor device department of the Berlin University of
Technology, an institution for research and development in the areas of
device simulation, technology, characterization, and reliability, with
special focus on device localization and repair from the backside of the
die. He received a diploma in physics and a Ph.D. in electrical engineering
on power devices, then joined Siemens AG’s Research Laboratories for Semiconductor
Electronics in Munich and has been a pioneer on photo-emission. He was
a delegate to the the joint IBM-Siemens 64M DRAM Development Team in East
Fishkill, N.Y., and until 2002 was director of failure analysis for Infineon
Technologies AG. He has contributed on various fields in technology, device
characterization, and analysis, with photoemission as a center of gravity.
On this topic he is a lecturer on ISTFA’s Seminar and in 1993 received
the German VDE-itg Award. He is member at large of the EDFAS board of
directors and a member of VDE (German Society of Electrical Engineering).
He serves on the ISTFA organizing committee (2002 general chairman), on
committees of ESREF and IPFA, and is chairing the EDFAS Publication Committee.
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 John Caffall
Director of Operations, Submicron Development Center (SDC); Spansion LLC
John Caffall is director of operations for the Submicron Development Center (SDC) at Spansion, the world's largest pure-play provider of Flash memory solutions. He is responsible for overseeing engineering, manufacturing and maintenance activities for the company's R&D center for advanced technologies for Flash memory. He holds an M.B.A. from San Jose State University and a B.S. in electronics engineering technology from the University of Houston.
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 Gilbert
Declerck
President and CEO, IMEC
Gilbert J. Declerck
is president and CEO of IMEC, Europe’s largest independent research center
in the field of microelectronics, nanotechnology, enabling design methods
and technologies for ICT systems. He authored and co-authored over 200
papers and conference contributions. He is a member of the Institute of
Electrical and Electronics Engineers (IEEE) and of the Electrochemical
Society. In 1993, he was elected Fellow of the IEEE for leadership and
contributions to metal-oxide-semiconductor device physics, charge coupled
device technology, and very large-scale integration processing techniques.
Prior to joining IMEC, he worked at the University of Leuven, where he
received his Ph.D. in electrical engineering in 1972 and became professor
in 1983. In 1984, when IMEC was founded, he moved to IMEC as vice president
of the advanced semiconductor processing division.
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 Alain Charles Diebold
Empire Innovation Professor of Nanoscale Science
AVS Fellow and Senior Member of IEEE
Alain recently became a professor at the College of Nanoscale Science and Engineering at the University at Albany. His research will focus on the impact of nanoscale dimensions on the physical properties of materials; he also continues to work in the area of nanoelectronics metrology. He is a member of the International Metrology Technical Working Group, founder and co-chair of the U.S. Metrology Technical Working Group for the 2007 International Technology Roadmap for Semiconductors, and chair of the Manufacturing Science and Technology Group of the American Vacuum Society. He was a SEMATECH Senior Fellow, with the main focus of his activities involving metrology industry coordination. He has edited the Handbook of Silicon Semiconductor Metrology, published in June 2001; is a Panel Member for the Metrology section of Future Fab International; and, he has co-edited three books that are conference proceedings from Characterization and Metrology for ULSI Technology and its predecessor conference. He also worked at Allied Signal in the areas of molecular beam epitaxy of III-V compounds and materials characterization of a broad range of semiconductor and amorphous metal products.
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 Giuseppe
Fazio
Advanced Process and Equipment Control Sr. Engineer, Numonyx
With a laurea degree in applied physics from Milan University, Giuseppe has working experience in several sectors, from research to industry, and vast experience in industrial and scientific instrumentation, as well as in the sector of components for industrial automation. After many years with ST Microelectronics, he is now in the R&D division of Numonyx. Giuseppe has authored and co-authored numerous articles, is an avid contributor at conferences and holds several patents in the semiconductor field.
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Paolo A. Gargini
Director of Technology Strategy for Intel Corporation
Dr. Paolo Gargini is the Director of Technology Strategy for Intel Corporation in Santa Clara, California. Dr. Gargini is also responsible for world-wide research activities conducted outside Intel for the Technology and Manufacturing Group by consortia, institutes and universities. Dr. Gargini was born in Florence, Italy and received a doctorate in Electrical Engineering in 1970 and a doctorate in Physics in 1975 from the Universita di Bologna, Italy, both with full honor and marks. He has done research at LAMEL in Bologna, Stanford Electronics Laboratory, and Fairchild Camera and Instrument Research and Development in Palo Alto from 1970 to 1977.Since joining Intel in 1978, Dr. Gargini has conducted studies on Process Reliability; he was responsible for developing the building blocks of HMOS III and CHMOS III technologies used in the 1980’s for the 80286 and the 80386 processors. In 1985 he headed the first submicron process development team at Intel. Dr. Gargini has been the Chairman of the Executive Steering Council (ESC) of I300I and, subsequently, of International Sematech from 1996 to 2000. He is now a member of the Sematech Board. Since 1998, Dr. Gargini has been the Chairman of the International Technology Roadmap for Semiconductors (ITRS). He is a member of various technical committees and technical advisory boards for organizations such as the Silicon Research Corporation (SRC), and the Technology Strategic Council (TSC) of the SIA in the US, IMEC in Europe, ASET and MIRAI in Japan. He also heads the International EUV Initiative (IEUVI), formed in 2001, that fosters cooperation and coordination among the largest EUV consortia in the world. Dr. Gargini is the facilitator of the International Consortia Cooperation Initiative (ICCI). This initiative, started in 2000, fosters exchange of information among a selected group of leading consortia and institutes in the world. In September 2003, Dr. Gargini was included by EE Times in a very selected group of Influencers of the semiconductor industry with the following motivation: “EE Times has chosen 13 people who are influencing the course of semiconductor development technology and taking it into realms that exceed the bounds set by the inventors of the transistor more than 50 years ago. With more than 25 years in the industry, Gargini is helping to navigate tough process and manufacturing waters.” Dr. Gargini initiated and became the first Chairman of the Governing Council of the Nano Electronics Research Initiative (NERC) funded in June 2005 by SIA. This Initiative is aimed at supporting and focusing research in universities toward subsequent commercialization of Nanoelectronics. NERC actively cooperates in this effort with USG organizations such as NNI, NSF, DARPA and NIST.
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 Janice M. Golda
Director, Lithography Capital Equipment Development; Intel
Janice Golda manages an organization responsible for creating strategies and working with Intel's lithography, mask and metrology suppliers and subsuppliers to deliver equipment meeting Intel's roadmap technology, capacity and cost requirements. She is a member of the Berkeley CXRO Advisory committee, is Chairman of the Board for the EUV LLC and holds one U.S. patent. She earned her B.S. in electrical engineering from Cornell University.
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 Steve
Greathouse
Global Microelectronics Process Technology Manager, Plexus Corporation
Steve Greathouse is the Global Microelectronics Process Technology manager at Plexus Corporation, in Nampa, Idaho, responsible for the development and deployment of microelectronic devices worldwide for Plexus. He has published many articles on technical topics related to semiconductor packaging, failure analysis and lead-free packaging. Steve has a B.S. in electronic physics from Weber State University with advanced studies in material science and computer science.
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 Daniel
J.C. Herr
Director of Nanomanufacturing Science Research, Semiconductor Research
Corporation
Daniel J.C. Herr leads
a team that provides vision, guidance and leveraged support for collaborative
university research in emerging nanoelectronics-related materials and
assembly methods, environmentally benign high-performance manufacturing,
and future factory technologies. He held senior engineering positions
at Honeywell Corporation during the VHSIC program, and Shipley Company,
in Japan, where he helped develop the SAL and DUV families of chemically
amplified photoresists and developers. He also founded AR&D Corporation,
a product design-consulting firm. Dr. Herr serves as adjunct associate
professor in materials science and engineering at North Carolina State
University, where he serves as a graduate thesis advisor and co-developed
and teaches a graduate level course on the materials science of nanoelectronics.
He also regularly teaches graduate-level courses on quality engineering.
Dr. Herr provides ongoing technical leadership for several of the Semiconductor
Industry Association’s Technology Working Groups, the EUV Consortium (concluded),
SPIE’s Metrology conference, as chair emeritus, and several other international
industry-related technical organizations. His publications cover topics
from mechanistic chemistry to strategic industry trends in nanoelectronics.
He also served as editor for several technical conference proceedings.
Dr. Herr created a suite of product optimization software, more robust
than Taguchi’s methodology, and is the inventor on several foundational
patents and disclosures in defect tolerant patterning, controlled nanotube
synthesis and placement, deterministic semiconductor doping, and ultimate
CMOS devices.
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 Davide A. Lodi
Wet Processes & Metrology Engineering Manager, Numonyx™
Davide Lodi graduated from Milan University in 1997, having studied solid state physics, with a thesis on shape memory alloys. Soon after, he joined STMicroelectronics, where he started as a process engineer; after becoming the manager of Wet Processes and Metrology Engineering at the NVM R&D site in Agrate, Italy, he moved to Numonyx, where he holds the same position. He has authored and co-authored several papers in both fields.
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 Raj
N. Master
Senior AMD Fellow, Chief Technologist, Advanced Micro Devices
Raj N. Master is senior
AMD fellow and chief technologist at AMD, which he joined in 1996. He
was responsible for successfully transferring the IBM C4/BGA technologies
to AMD and set up highvolume manufacturing in Penang, which has produced
more then 100 million flip chip assemblies to date. He led the organic
packaging development and manufacturing, which is now in high volume production.
He provides technical guidance for equipment and processes for C4/BGA
manufacturing lines in Penang and Singapore. He also provides technical
expertise and guidance to product lines, failure analysis, reliability
and quality organizations within AMD. He manages the advanced packaging
group involved in developing strategic enabling technologies and is also
manager of the lead-free program of AMD. Raj joined AMD after spending
21 years at IBM, where he was a senior technical staff member. He was
technically responsible for packaging development and manufacturing as
related to C4, ball grid array, column grid array, board level reliability
and multilayer ceramic substrate. He has 36 US patents issued to him and
has published over 70 technical papers.
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 Peter
Rabkin
Director of Device and Process Technology, Sandisk Corp.
Dr. Peter Rabkin is currently director of Device and Process Technology at Sandisk Corp. focusing on development of novel 3D memory technologies and products. Before that, he served as program director for Advanced Technology Development at Xilinx, Inc., responsible for process-to-design integration and DFM. Prior to Xilinx, Dr. Rabkin was director of Advanced Technologies at PDF Solutions, Inc., and held a number of other senior managerial and technical positions, including roles at Hynix Semiconductor, Hyundai Electronics and Silvaco International. With over two decades in the semiconductor industry, he was involved in the development and transfer to volume production of a wide variety of semiconductor processes, devices and products, spanning from cutting-edge CMOS, to advanced memories, to devices of power electronics and high-performance heterojunction applications. Dr. Rabkin is currently an elected member of the IEEE SCV Electron Device Society Committee, and has been an editorial panel member and contributing editor of Future Fab International since 2005. He has authored and co-authored over 80 publications, and has been an invited presenter and panel member at numerous reputable technical and business forums. He also holds 13 U.S. patents. Dr. Rabkin holds a master's degree in physics from Tartu University and a Ph.D. in physics of semiconductors from the St. Petersburg Institute of Physics and Technology.
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Peter Ramm
Head of Dept. Si Technology and VSI, Fraunhofer IZM, Munich
Peter Ramm received the physics and Dr. rer. nat. degrees from the University of Regensburg. He worked for Siemens in the DRAM facility and joined Fraunhofer in 1988 focusing on 3D integration technologies. Dr. Ramm is head of the Silicon Technology and VSI department at Fraunhofer IZM, Munich. He has authored over 50 papers and 20 patents, and is editor of the Handbook of 3D Integration (Wiley-VCH).
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 Ernst
Richter
Technology Transfer Manager, Inotera Memories / Qimonda
Ernst Richter is transfer manager at Inotera Memories, a joint venture between Qimonda (previously Infineon Technologies) and Nanya Technologies in Taiwan. He joined Inotera at its start-up in 2003 as Infineon delegate for DRAM technology transfers. Previously, he worked at Infineon SC300 as site representative supporting technology synchronization within Infineon’s global DRAM fab cluster. Prior to Infineon Dresden he spent more than four years on material research for pioneering lithography at Infineon Erlangen. His professional employment in semiconductors started in 1998 at the Siemens Erlangen research center. He holds a Ph.D. and an M.Sc. in chemistry from the University of Regensburg and an M.Sc. in materials science from the University of Kent at Canterbury.
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 Klaus-Dieter
Rinnen
Director/Chief Analyst, Dataquest
Klaus-Dieter Rinnen
is director for Dataquest’s semiconductor and electronics manufacturing
group, which covers trends and competitive positioning in semiconductor
capital equipment, materials, contract manufacturing (foundry and SATS),
and electronics manufacturing services. Before joining Dataquest, he was
at Applied Materials and AT&T Bell Laboratories. He earned a diploma degree
in physics with minors in physical chemistry and mechanical engineering
in Germany and a Ph.D. in applied physics from Stanford University.
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 John
Schmitz
Vice President, NXP Semiconductors Research
John Schmitz is a VP of NXP Research and oversees research activities in IC process and device technologies. Prior to that, he served as VP and COO for manufacturing technology of SEMATECH from April 2002 to December 2005. There he launched the Advanced Technology Development Facility (ADTF) for-profit subsidiary as well as the International SEMATECH Manufacturing Initiative (ISMI) subsidiary. Prior to coming to SEMATECH, he served as vice president and general manager of MOS4YOU in the Netherlands, Philips Semiconductors' advanced development and manufacturing unit for embedded nonvolatile memories. Schmitz joined Philips Research Labs in 1984, where he worked on various interconnect systems for advanced integrated circuits. After that he served as a director of process development at Genus Inc. He worked for two years in the joint ST-Philips development center in Crolles, France, in the development and manufacture of planarization techniques and dielectric materials as a group leader. Schmitz holds a master's degree in chemistry from Radboud University of Nijmegen, Netherlands, and a doctorate in physical chemistry from Radboud University Nijmegen. He has authored more than 45 papers in various scientific journals and has written books on IC technology, titled Chemical Vapor Deposition of Tungsten and Tungsten Silicides for VLSI/ULSI Applications, and on thermodynamics titled The Second Law of Life. He holds six patents in the areas of PECVD-TiSi2 and CVD-W.
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 Steven
E. Schulz
President and Chief Executive Officer
Silicon Integration Initiative, Inc.
Since 2002, Steve Schulz has served as president and CEO of Si2, the leading worldwide consortium of semiconductor and software companies chartered to develop EDA standards.
Steve was previously VP of corporate marketing for BOPS Inc. and was employed by Texas Instruments for 19 years. At TI, Steve was a Senior Member of the Technical Staff and held a wide variety of management and technical positions, including CAD strategy manager and reliability strategy manager. Representing TI, he served as chairman of the Design Sciences Technical Advisory Board for Semiconductor Research Corporation. He has vast experience in standards, having served as president of VHDL International, co-chairman of Accellera, and chairman of the VITAL and SLDL/Rosetta standards initiatives. He has authored more than 150 articles on EDA and IC design methodology, and was a founding editor of Integrated Systems Design magazine. Steve has served on numerous boards, including CADstone Inc., SCDSource.com, ProphICy Semiconductor and CMP Publications.
Steve has a Bachelor of Science degree in electrical engineering from the University of Maryland at College Park, and an M.B.A. from the University of Texas at Dallas. He is an active jazz trombone musician in the Austin area.
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 Alan
Weber
President, Alan Weber and Associates
Alan Weber is the
president of Alan Weber and Associates, a consulting company specializing
in semiconductor advanced process control, e-diagnostics, and other related
manufacturing systems technologies. Before founding his own company, he
was the vice president/general manager of the KLA-Tencor Control Solutions
division, acquired from ObjectSpace in March 2000. While at ObjectSpace,
he was responsible for all aspects of the company’s semiconductor manufacturing
systems business, including development of the APC framework and its eventual
commercialization and global marketing/deployment as the Catalyst APC
product. Before joining ObjectSpace in early 1997, he spent eight years
at SEMATECH and was responsible for advanced manufacturing systems and
related standards R&D, including the CIM framework. Before that, he spent
16 years at Texas Instruments managing a variety of technology programs
in the semiconductor CAD and industrial automation/control businesses,
including a four-year tour of duty in Europe. He holds bachelor’s and
master’s degrees in electrical engineering from Rice University.
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 Jeff
Wetzel
Senior Member, Technical Staff, SVTC, LLC
Dr. Jeffrey (Jeff) T. Wetzel was recently appointed to the role of senior member of the Technical Staff of SVTC, LLC in Austin, Texas. His previous experience includes material characterization, tool, process and device integration at IBM, Motorola, SEMATECH, and Tokyo Electron in engineering and management roles in silicon microelectronics R&D since 1983.
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 Kazuyoshi "Kazu" Yamada
VP, Custom SoC Solutions Strategic Business Unit, NEC Electronics America, Inc.
Kazu Yamada oversees the company's custom ASIC-related business as well as engineering and system memory and power management business. In his 25-plus years with NEC companies, he has held several key positions in marketing and engineering. Mr. Yamada holds bachelor's and master's degrees in electrical engineering from the Musashi Institute of Technology in Tokyo and holds 20 patents in Japan for bipolar-related designs.
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 Ehrenfried
Zschech
Manager, Center of Complex Analysis, AMD Saxony
Ehrenfried Zschech is manager of the Center of Complex Analysis at AMD in Dresden, which he joined in 1997. His responsibilities include the analytical support for process control and technology development, as well as physical dailure analysis. He received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. After having spent four years as a project leader in the field of metal physics and reliability of microelectronics interconnects at Research Institute of Non-Ferrous Metals in Freiberg, he was appointed as a university teacher for ceramic materials at Freiberg University of Technology. In 1992, he joined the development department at Airbus GmbH in Bremen. There he managed the metal physics group and worked on laser-joining metallurgy of light metals. His current research interests are in the areas of thin film materials compatibility, structure and materials analysis and physical failure analysis in integrated circuit applications. He has published three books and more than 100 papers in scientific journals in the areas of solid-state physics and materials science. He is honorary professor for nanomaterials at the Brandenburg University of Technology in Cottbus, Germany.
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