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 It’s not just a wafer... it’s a yield improvement up to 10%. Future Fab Intl. Volume 23, July 09, 2007
Step-function improvement in gettering consistency. Effectively getter high levels of metals such as Cooper, Nickel, and Iron. Eliminate steps that are likely to add metal contamination. Demonstrated gettering in next generation low thermal budget processes. Drop-in capability.
Section 5 Introduction: Wafer Processing Future Fab Intl. Volume 23, July 09, 2007
For the past 40 years the semiconductor industry has progressed by aggressively scaling horizontal dimensions to increase transistor density at the pace outlined by Moore’s Law. Vertical dimensions have also been accordingly scaled down to balance transistor electrical performance.
Paolo Gargini, Intel Corporation, Ernst Richter, Inotera Memories / Qimonda
3D Integration Technologies for Ultrasmall Wireless Sensor Systems – the e-Cubes® Project Future Fab Intl. Volume 23, July 09, 2007
As advanced microsystems, e.g., electronic
sensor systems, are becoming
more complex and individualized, standard
state-of-the-art approaches will not
be appropriate anymore to meet future
objectives.
Peter Ramm, Fraunhofer IZM (et al.), Anton Sauer, Fraunhofer Institute for Reliability and Microintegration IZM
FinFETs: Challenges in Material and Processing for a New 3D Device Paradigm Future Fab Intl. Volume 23, July 09, 2007
CMOS scaling as we approach the
22nm node and beyond has turned to
new devices and materials as a means to
keep the performance gains and physical
device shrinks at a constant historical
pace.
H. Rusty Harris, SEMATECH, Muhammad Mustafa Hussain, SEMATECH, Casey Smith, SEMATECH, Ji-Woon Yang, SEMATECH, Prashant Majhi, SEMATECH, Hemant Adhikari, SEMATECH, Hsing-Huang Tseng, SEMATECH, Raj Jammy, SEMATECH
Repeatedly Lucky? Future Fab Intl. Volume 23, July 09, 2007
The extent of the material change in SC
chips brings significant opportunities for
gambling: Hf or Zr?, ALD or CVD?, batch or
single wafer, O3 or H2O, TEMAH or
TDEAH? These are the choices that our customers
are making every day, and just for
one application.
Spin-On Glass (SOG) Used as a Gap-Filling Process in Future DRAMs Future Fab Intl. Volume 23, July 09, 2007
To reduce the manufacturing cost of
DRAMs, higher storage densities, with
smaller cell area are produced for every
technology node. To meet the requirements
of high density, the DRAM structure
has been extended into the third
dimension with stacked or deep-trench
(DT) capacitors.
Arabinda Das, Qimonda, Peggy John, Qimonda, Hans-Peter Sperlich, Qimonda
When Other Graphite Materials Hit the Wall, Poco Graphite Breaks Through Future Fab Intl. Volume 23, July 09, 2007
Ten years ago, many people believed
that graphite materials and their usefulness
in semiconductor applications
would soon hit the wall. Today graphite
materials continue to be used as preferred
component materials in many
types of semiconductor manufacturing
equipment.
In order to provide next-generation
equipment that offers a technology
advantage for its customers at an economic
price, equipment manufacturers
continually seek the best component
materials and eliminate troublesome
materials that reduce the uptime of equipment.
Graphite, along with metals, was
one of several component materials that
industry experts predicted would not be
able to meet the challenge of the new
processes. Were their predictions wrong?
Well, yes and no.
Incorporating BEOL Effects in IC Performance Characterization Future Fab Intl. Volume 22, January 09, 2007
With ever-shrinking device sizes, the
interconnect delay is becoming a significant
contributing factor to the overall
delay. This trend is escalating the impact of
back-end-of-line (BEOL) parameters on
performance. To accurately project product
performance in future generations of
processors, it is essential to develop a systematic
approach to optimize BEOL
parameters. To be able to achieve this, the
timing analysis tools should be able to provide
insight into the BEOL parameters
affecting the delay of a speed path.
Presently, there is a need to incorporate
models into the current timing analyzer to
correctly account for the various process
distortion effects and thermal effects. Also,
BEOL speed sensitivity and development
of new test structures for BEOL impact on
performance needs to be investigated.
Michael Z. Su, Advanced Micro Devices, Pratibha B. Singh, Advanced Micro Devices, Jaime C. Bravo, Advanced Micro Devices, Lei Fu, Advanced Micro Devices
CMOS Scaling Beyond High-k and Metal Gates Future Fab Intl. Volume 22, January 09, 2007
Historically, CMOS scaling has provided
the means to realize higher performance
with every technology node. At
each node, there always existed severe
skepticism of the ability to realize future
generations by simply scaling the geometry
of the devices. Interestingly, technologists
almost always have managed to
scale the devices with minimal change to
the conventional CMOS process flow.
However, scaling has clearly reached fundamental
material limits, especially for
gate oxide, and hence we now are in the
era where further scaling can be realized
mainly by new materials and/or device
architecture. In order to be well-prepared
with options to continue scaling during
such a scenario, nearly a decade of
research and development has been conducted,
by various groups, on high-k gate
dielectrics to potentially replace SiON for
future generation CMOS. There has been
excellent progress in recent years in
demonstrating high- performance
devices with hafnium-based high-k dielectrics.[1,2] However, during these
investigations, it became clear that highk
dielectrics were incompatible with the
poly Si gate electrode (due to Fermi-level
pinning issues) especially for high-performance
devices.[3] Although several
recent papers show very promising
results, there has been limited consensus
on both the candidate material systems
for metal gate application and their
potential integration in nodes that would
first realize the implementation of high-k
dielectrics.[1,4,5] While the introduction
of high-k/metal gates has been delayed,
CMOS scaling with increased performance/
node is being realized primarily
by straining the Si channels to produce
higher career mobility, and hence drive
currents.[6] This article provides an outlook
of the some of the primary challenges
and opportunities that lie ahead to
keep up the scaling roadmap beyond
high-k/metal gates. Also, SEMATECH
achievements in these areas are appropriately
highlighted. Note: the formation
and effect of process-induced strain,which is device geometry/architecturespecific,
is not discussed in this paper.
Prashant Majhi, SEMATECH, Pankaj Kalra, SEMATECH, H. Rusty Harris, SEMATECH, Jungwoo Oh, SEMATECH, Muhammad Mustafa Hussain, SEMATECH, Hsing-Huang Tseng, SEMATECH, Raj Jammy, SEMATECH
ALOHA™: It’s All About Partnerships! Future Fab Intl. Volume 22, January 09, 2007
Fast and effective introduction of novel
chip materials requires key collaborations
between device manufacturers (IDM),
equipment manufacturers (OEM) and the
precursor suppliers. The precursor supplier
designs chemistries that are used in the
processes developed by OEMs and IDMs.
These individual process bricks are eventually
integrated in a manufacturing
process flow by the IDM.
Comparison of Deposition Temperature Measurement Methods for HDPCVD and PECVD Silicon Dioxide Films Future Fab Intl. Volume 21, July 01, 2006
High density plasma (HDP) and plasma
enhanced chemical vapor deposition
(PECVD) are widely used techniques in
semiconductor integrated circuit (IC)
manufacturing to obtain un-doped silica
glass (USG) thin films, especially to form
inter-metal dielectric (IMD) stacks, even
into 90nm semiconductor technology
node. Thin films from PECVD and
HDPCVD can be deposited with a range of
temperature between 300 to 750°C,
according to their different applications
inside the integration process flow.
Temperature is an important parameter
to be kept under control to attain repeatable
deposited thin films and avoid circuit
defects such as metal bus hillock formations,
dielectric cracks and low-k material
de-cohesion.
So it becomes crucial to use different,
complementary and indirect measurement
methods to maintain controlled
temperature during reaction and, consequently,
film chemical-physical characteristics:
TiAl3 alloy formation method, [Si-
OH] bond concentration by Fourier transform
infrared spectroscopy, wet etch rate
(WER) and in situ pyrometer or thermocouple
readings.
Gianluca Gulleri, STMicroelectronics , L. Battan, STMicroelectronics , Luca Zanotti, STMicroelectronics
WAFER PROCESSING SECTION 6 – INTRODUCTION Future Fab Intl. Volume 21, July 01, 2006
SEMATECH researchers, on assignment
from TI, Intel and IBM, report on an ingenious
new way to reduce the threshold voltage of
CMOS devices by adjusting the value of the effective
work function in devices using Hafnium (Hf)
oxide as gate dielectric in conjunction with an
upper metal gate electrode. It had been previously
reported that some form of Silicon oxide is typically
present between the silicon substrate and the Hf oxide. Indeed, despite the use of many different
metals, the authors were not able to
reduce the effective work function below 4.2eV
or enhance it above 4.8eV for NMOS and PMOS
respectively. However, by introducing a thin
layer containing either Lanthanum (La) or
Aluminum (Al) underneath the Hf oxide layer,
they were able to reduce the effective work function
to about 4.05eV and enhance it to about 5eV
for NMOS and PMOS devices respectively. Holes
and electron mobilities of value about 80 to 90
percent of the universal mobility were demonstrated.
It is speculated that charges induced by
the described process at the interface between
the Silicon oxide layer and the Hf/Al (or Hf/La)
oxide layer are responsible for the effects on the
effective work functions.
Paolo Gargini, Intel Corporation, Ernst Richter, Inotera Memories / Qimonda
Work Function Engineering Using Interfacial Layers on Hf-Based Gate Dielectrics Future Fab Intl. Volume 21, July 01, 2006
We review a new approach that has
been recently reported to realize bandedge
work functions on Hf-based gate
dielectrics.[1-5] The approach relies on
using thin Al-based or La-based interfacial
layers inserted between the Hf-based
gate dielectric and the metal gate, resulting
in n-type and p-type effective work
functions (~4.05 and 5.1 eV), respectively.
We demonstrate that transistors can be
fabricated with threshold voltages as low
as 0.25V for NMOS and -0.45V for PMOS,
electron and hole mobilities of 80 to 90
percent of the universal SiO2 curve, and
equivalent oxide thickness of 1.2nm to
1.3nm. A model for the observed work
function enhancement is presented.
Finally, implications of this approach to
metal gate integration are discussed.
Husam N. Alshareef, Texas Instruments Incorporated, Prashant Majhi, SEMATECH, M.A. Quevedo-Lopez, SEMATECH, Raj Jammy, SEMATECH, B.H. Lee, IBM, P. Kirsch, Intel Corporation
ALD vs. MOCVD for High-k Deposition in 45nm CMOS and Below Future Fab Intl. Volume 20, January 07, 2006
With the transition toward the 45nm
CMOS node and beyond, the gate stack is
submitted to some revolutionary changes.
The introduction of high-k materials as new
gate dielectric is a target that must definitely
be reached. Also, for the gate electrodes a
number of novel options are under investigation.
One constant throughout this evolution
toward new materials is the choice of
an appropriate deposition technique; the
two major options being atomic-layer-based
and metal-organic-based chemical-vapor
deposition (ALD or MOCVD). IMEC has
investigated and optimized implementations
of both deposition techniques in great
detail in strategic collaboration with several
tool vendors and therefore is in a privileged
position to report on both deposition techniques
for future gate stack applications.
Wim Deweerd, imec, Annelies Delabie, imec, Sven Van Elshocht, imec, Stefan De Gendt, imec, Matty Caymax, imec, Marc Heyns, imec
Low-K Damage Challenges Impacting Attainment of Keff = 2.5 Future Fab Intl. Volume 20, January 07, 2006
The 2005 ITRS Roadmap calls for the use
of porous ultra-low-K (p-ULK) dielectric
materials to achieve a Keff < 2.6 for the 45nm
node.[1] SEMATECH’s modeling of the effective
K of the dielectric stack includes all films
in which the metal line is embedded (etch
stop, bulk dielectric, hard mask (HM) and
cap are combined). Dielectric films above
and below the hard mask and stop layer are
included in the model.[4]
Eric Busch, SEMATECH, Brian White, SEMATECH, Ricky McGowan, SEMATECH, Sharath Hosali, SEMATECH, Sri Satyanarayana, SEMATECH
New Optical Range Inspection and Improving Optical Response for Spectroscopic Base Endpoint Detection Future Fab Intl. Volume 20, January 07, 2006
To achieve continuous advances in
semiconductor manufacturing, accurate
in-situ techniques and diagnostics must
be developed for optimum process control,
as in the case of dry etching endpoint
detection. Optical emission spectroscopy
is one of the most widely used plasma
processing diagnostics, since it is nonintrusive
and provides real time process
data. In current practice only UV-VIS
range is used for endpoint detection.
Unfortunately, this emission range, corresponding
to electronic transitions of
molecular or atomic levels, sometimes
does not give clear and employable
results, especially when areas to be patterned
become very small and etching
selectivity cannot be easily achieved. In
this article we propose and evaluate a
new method to detect optical endpoint.
The new method involves use of emission
bands laying into the IR portion of the
spectra, (corresponding to molecular
vibrational modes) in parallel with optical
emission intensity improvement of these
bands, by introducing a suitable inert gas
(hereinafter called the enhancer). OES
data, main process parameters and morphological
characterization will be discussed
to prove the efficiency of the proposed
method in the patterning of small
trenches of 60nm of depth into a SiN layer
deposited over SiO2.
Giuseppe Fazio, Numonyx, Pietro Petruzza, STMicroelectronics , Alessandro Spandre, STMicroelectronics
SECTION 6 – INTRODUCTION: WAFER PROCESSING Future Fab Intl. Volume 20, January 07, 2006
Advanced materials and processes for future
nodes have to be thoroughly investigated in
advance to ensure timely manufacturability.
Readjustments allow continuous learning whereas
novelties require early learning. The ITRS is a
dynamic assessment of the semiconductor technology
requirements with a long-term scope.
Technological challenges are identified and timed
in view of industry needs. And some revolutionary
innovations are on the roadmap! This issue of
Future Fab International addresses ITRS challenges
for process and material interactions as well as a
selected process control at front end processing.
Ernst Richter, Inotera Memories / Qimonda
SECTION 6 – INTRODUCTION: WAFER PROCESSING Future Fab Intl. Volume 20, January 07, 2006
In this issue of Future Fab International,
you will find exciting new reports on improved
end-point detection methods used during the
etching of SiN trench patterns with very small
exposed areas, important findings on new
ways of characterization and reduction of
damage in the preparation of ultra-low-k
materials and also an important side-by-side
comparison between ALD and MOCVD deposition
techniques for high-k gate dielectrics for
CMOS processes aimed at 45nm and below.
Paolo Gargini, Intel Corporation
Effects of Plasma Etch and Stripping on ULK Materials Future Fab Intl. Volume 19, June 28, 2005
Nanoporous silica (NPS) materials are
compelling candidates for future microelectronic
and optoelectronic applications
requiring ultra-low dielectric constant
(ULK) and /or refractive indices, respectively.
Porous materials provide the ability
to control porosity and hence tailor the
performance of the material to meet the
requirements of future generations of integrated
circuits. The nanoscale pores of
NPS material are created by the removal of
organic groups, a sacrificial phase, from
the silica matrix. Porosity reduces thermal
and mechanical properties of NPS materials
as compared with silicon dioxide.
Materials transport also becomes easier in
the porous structure. These issues make
the integration of porous material into
back-end-of-line devices challenging.
Xuefeng Hua, University of Maryland, Gottlieb S. Oehrlein, University of Maryland, Paolo Lazzeri, ITC-irst, Erica Iacob, ITC-irst, Mariano Anderle, ITC-irst, T. S. Kuan, University at Albany, SUNY, Ping Jiang, Texas Instruments Incorporated, Wen-li Wu, National Institute of Standards and Technology, C.K. Inoki, University at Albany, SUNY
Gate Electrode Development for Dual Metal-Gate CMOS Applications Future Fab Intl. Volume 19, June 28, 2005
A review of the Sematech metal gate
program activities is presented. In particular,
we describe a standardized terraced-
oxide technique that has been
developed to accurately extract the effective
work function of metal gates. It is
shown that the technique gives work
function values that match well with
those extracted from transistor device
threshold voltage. Furthermore, the technique
has been used to evaluate several
different types of metal gates including
pure metals, metal alloys, ternary metal
systems and the various factors that control
their work function. Metal gates with
work function values ranging from 4.1 to
5.0 eV have been demonstrated, making
them attractive candidates for future generation
CMOS gate electrodes. In addition,
dual metal-gate functional CMOS
devices with Lg down to 85 nm have been
demonstrated.
Husam N. Alshareef, Texas Instruments Incorporated, Zhibo Zhang, Texas Instruments Incorporated, Prashant Majhi, SEMATECH, George A. Brown, International SEMATECH, P.M. Zeitzoff, International SEMATECH, Howard R. Huff, International SEMATECH, B.H. Lee, IBM
Introduction: Wafer Processing Future Fab Intl. Volume 19, June 28, 2005
The semiconductor industry has undertaken
the task, in the last few years, to replace
several steps of the workhorse CMOS process
in order to further scale down device features
and, by so doing, remain on Moore’s Law.
Paolo Gargini, Intel Corporation, Ernst Richter, Inotera Memories / Qimonda
Seed Enhancement: A Bridging Technology Future Fab Intl. Volume 19, June 28, 2005
With ultra-large-scale integration
progress, efficient copper metallization of
the narrow features becomes challenging.
Among the elementary steps involved in
the metallization sequence, the most critical
will probably be the deposition of a
copper seed layer necessary to initiate the
bulk copper electrochemical deposition
(ECD). For future generations, physical
vapor deposition (PVD) techniques that are
currently employed will reasonably reach
a limit, as they are not able to perfectly
cover the sidewalls of the features. The
resulting discontinuous seed layers can
cause defects such as voids in the copper
lines and contact holes. To overcome this,
“seed enhancement” or “seed repair” techniques
have been proposed, which are
able to bridge the local discontinuities of
the copper PVD layer. In this article, this
concept is illustrated through the example
of an electrodeposition process called ECD
seed™. The benefits of this approach are
demonstrated, and the remaining challenges
are discussed.
Paul-Henri Haumesser, Ph.D., CEA-Leti, Anne Roule, CEA-Leti, Sylvain Maîtrejean, Ph.D., CEA-Leti, Gérard Passemard, Ph.D., STMicroelectronics
An Improved Wet Cleans Method For 90 nm Node – Semiconductor Processing Technology Future Fab Intl. Volume 18, January 12, 2005
Wet cleaning for polymer removal has
become more challenging with the continuous
increases in density and number
of interconnects and shrinkage of feature
sizes in the semiconductor industry.
Amine-based chemistries such as EKC
are the most commonly utilized solution
for removal of post etch residues from
vias, contacts and metal lines[1-6].
Cleaning solutions are introduced into the
cleaning chamber using spray nozzles
on the side of the chamber. The Semitool
SST batch solvent processing tool
removes etch polymer residues commonly
left behind at the sidewall and
bottom of the contacts (or vias) and on
the surfaces of the metal lines and the
spaces between them. Good via cleaning
is important to avoid via glue layer
coverage issues that can result in open
via issues. Good metal line cleaning is
important to avoid shorts between the
lines and reliability failures.
Michael Gu, Cypress Semiconductor, Jie Zhang, Cypress Semiconductor, Rick Foley, Cypress Semiconductor, Owen Gower, Cypress Semiconductor, Brian Gardner, Semitool
Inotera – Efficient Transfer Within Infineon’s Global Fabrication Cluster Future Fab Intl. Volume 18, January 12, 2005
This article is a follow-up on a previously
published article[1] that introduced
Infineon’s fab cluster concept and outlined
results for the 140 nm dynamic randomaccess
memory (DRAM) technology. This
time technology transfer and qualification
of the 110 nm DRAM technology is
highlighted for the Inotera Memories joint
venture in Taiwan. Inotera was founded in
2003 as a fifty-fifty 300 mm joint venture
between Nanya Technology and Infineon
Technologies. Technology transfer was
done from Infineon’s Semiconductor 300
mm fab (SC300) in Dresden, Germany,
whereas qualification was completed in a
joint manner by both venture partners.
Ernst Richter, Inotera Memories / Qimonda, Vasudeva Reddy, Inotera Memories / Qimonda, Giorgio Schweeger, Infineon Technologies AG, Karl-Heinz Thürer, Infineon Technologies AG
Integration Of High-k Gate Dielectrics And Dual Work Function Metal Gate Electrodes Future Fab Intl. Volume 18, January 12, 2005
The high gate leakage of nitrided SiO2
(SiON) and the depletion of polysilicon
gate electrodes limit their usefulness in
advanced complementary metal oxide
semiconductor (CMOS) devices. Advanced
high-performance devices require high
dielectric constant (high-k) gate dielectrics
and dual work function metal gate
electrodes to address these challenges.
Although there has been a multitude of
high-k gate dielectric materials investigated
to date, the community is focusing
on Hf-based materials such as HfO2,
HfO2/SiN, and HfSiON.[1,2] While the
industry is converging on the high-k gate
solution, it is not yet united behind a
single approach for dual work function
metal gates.
Luigi Colombo, Texas Instruments Incorporated, Mark Visokay, Texas Instruments Incorporated, Jim Chambers, Texas Instruments Incorporated
SECTION 6: INTRODUCTION Future Fab Intl. Volume 18, January 12, 2005
Technology requirements continue to
become more stringent in the nano-scaling
integration era (below 100 nm feature size) as
predicted by the International Technology
Roadmap for Semiconductors. Yield enhancement
is becoming more difficult as wet chemicals
struggle to penetrate sub-100 nm spaces.
Furthermore, the geometrical scaling laws
outlined in the mid-’70s that have so successfully
guided the technology engineers for the
past 25 years need to be revised because the
basic materials, at the foundation of the CMOS
process, are reaching fundamental limits. New
approaches to scaling have been identified, and new solutions are making their way into the
CMOS process to support the doubling of
components every two years predicted by
Gordon Moore in 1975.
Paolo Gargini, Intel Corporation, Ernst Richter, Inotera Memories / Qimonda
Sowing The Seeds For Larger Cu Grains In Narrow Cu Wires Future Fab Intl. Volume 18, January 12, 2005
The resistivity of copper interconnect
lines has become a growing concern
in light of the continuous scaling of
semiconductor components. A marked
increase is observed for decreasing
dimensions, rendering it impossible to
adhere to the 2.2 µW-cm target set in
the ITRS roadmap for future technology
nodes. However, even though several
effects are claimed to be significant, the
relative contributions of various physical
effects that can contribute to this
increase are unclear. This is partly due
to the fact that theories on surface (Fuchs-
Sondheimer[1,2]) and grain boundary
(Mayadas[3]) scattering predict similar
dependencies on layer thickness, and
both have unknown phenomenological
parameters (p and R respectively).
Sywert H. Brongersma, imec, Gerald Beyer, imec, Karen Maex, imec
Advanced Methods of Producing Ultra-Pure Silicon Carbide Products Future Fab Intl. Volume 17, June 21, 2004
Silicon carbide (SiC) has been utilized as
a base material for various components in
process tools employed in the manufacturing
of semiconductor devices. High heat
processes that require a stable base material
at elevated process temperatures have
exploited the thermal stability and conductivity
characteristics of silicon carbide. Diffusion
and rapid thermal process (RTP) have
been the dominant process applications for
which SiC materials have been recently used.
Andrew Sleutjes, RTS Spares, Hiroaki Wada, Bridgestone Corporation
Low-k Dielectrics: Spin-On or CVD? Future Fab Intl. Volume 17, June 21, 2004
The introduction of low-k dielectrics into
manufacturing is progressing slower than
expected. Lowering the k value remains an
important issue, and the debate on the
ultimate low-k material – spin-on vs.
chemical vapor deposited – is still ongoing.
A few years ago, the competition was in
favor of spin-on deposited materials with k
values as low as 2.0, the requirements on k
values at that time being very demanding.
Recently, however, the feasibility of
depositing low-k materials with a k value
below 2.4 has been demonstrated, but
problems with the implementation of
materials with such low k values, in general,
have delayed the entering of low-k
dielectrics in production.
Mieke Van Bavel, imec, Francesca Iacopi, imec, Mikhail Baklanov, imec, Karen Maex, imec
Low-k Dielectrics: Was the Roadmap Wrong? Future Fab Intl. Volume 17, June 21, 2004
The Interconnect chapter of the 1994
U.S. National Technology Roadmap for
Semiconductors (NTRS) described the first
needs for new conductor and dielectric
materials that would be necessary to meet
the projected overall technology
requirements and reduce RC delays. At that
time, even the most optimistic implementation
of a new dielectric and the use of
copper uninhibited by-barriers would not
have provided the needed improvement in
signaling speed to meet anticipated
microprocessor chip speeds.
Christopher Case, Solid State Solutions
Plasma Damage and Pore Sealing: Increasingly Coupled ULK Integration Challenges Future Fab Intl. Volume 17, June 21, 2004
Ultra-low-k (ULK) dielectrics pose a host of
integration challenges due to their porosity
and increased susceptibility to physical and
chemical modification from plasma
processes. As the semiconductor industry
moves toward ULK, back-end of line (BEOL)
unit processes will become more coupled
than ever before as each process must take
into account how it will change the
properties of the ULK. It has been shown
that plasma processes play a significant role
in pore sealing, as well as film densification
and chemical modification. While integration
of nondamaging plasma processes helps
mitigate electrical performance degradation,
the need for a viable pore-sealing solution
still remains.
Sameer K. Ajmera, Texas Instruments Incorporated, Phillip D. Matz, Texas Instruments Incorporated, Jinyoung Kim, Texas Instruments Incorporated, Patricia B. Smith, Texas Instruments Incorporated, Stephan Grunow, Texas Instruments Incorporated, Satyavolu S. Papa Rao, Texas Instruments Incorporated, Changming Jin, Texas Instruments Incorporated, Trace Q. Hurd, Texas Instruments Incorporated
Section 6 Introduction, Vol. 17: Wafer Processing Future Fab Intl. Volume 17, June 21, 2004
In this issue you will find an exciting review
of the challenges and successes encountered in
the development and integration of low-k
dielectrics films into advanced multilayer
metallization processes. You will also learn about
new techniques developed for the production of
high-quality SiC.
Paolo Gargini, Intel Corporation
Achieving Fast Technology Transfer, Ramp, and Yield Improvement – Infineon’s Fab Cluster Concept Future Fab Intl. Volume 16, February 03, 2004
Infineon’s fabrication (fab) cluster concept ensures global production ramp focusing on the profitable dynamic random-access memory (DRAM) product lifecycle. Especially commodity products, like the 256Mb D14, are the vehicles for the introduction of the newest technology and synchronization of the fab cluster. The production line is responsible for the highest-volume products with the focus on low production costs and small chip sizes.
Ernst Richter, Inotera Memories / Qimonda, Giorgio Schweeger, Infineon Technologies AG
An ITRS View on Future Factory Integration, Design, and Capabilities Future Fab Intl. Volume 16, February 03, 2004
The need for future breakthrough technologies and capabilities that radically improve semiconductor factory design and manufacturing has never been greater.
Jeffrey S. Pettinato, Intel Corporation
Developing a WSix Gate Etch Process with CD Bias Uniformity less than 3 nm Future Fab Intl. Volume 16, February 03, 2004
Shrinking device geometry and differing material properties pose challenges for the gate etch process at 130 nm and below. A 300 mm hardmask (HM) WSix gate etch process is developed that achieves the desired WSix and poly profiles, good selectivity to the HM, and CD bias uniformity of < 3 nm (3ó). A CF4/Cl2/N2 chemistry main etch (ME) etches the Wsix layer to endpoint plus a certain over-etch percentage. The remaining poly film is etched with a HBr/Cl2/HeO2 chemistry soft-landing (SL) step until the poly layer starts to clear. Poly residue is removed using a HBr/HeO2/He over etch (OE). The effects on CD bias tuning of N2 flow, bias power, HeO2 flow, and WSix OE percentage are discussed.
Wilfred Pau, Applied Materials, Meihua Shen, Applied Materials, Shashank Deshmukh, Applied Materials, Takanori Nishizawa, Applied Materials
SECTION 5 INTRODUCTION, VOL 16: Wafer Processing Future Fab Intl. Volume 16, February 03, 2004
Manufacturing requirements continue to become more stringent
as device dimensions continue to decrease. In order to maintain
and improve cost effectiveness it is necessary to tighten
process specifications and, as a result, brand new processes
need to be developed. Use of 300 mm wafers is mandatory in
order to reduce costs. Yield improvement and reduced cost
must be pursued each single operation.
Paolo Gargini, Intel Corporation
Solving Problems Leads to Next-Generation Consumables in Ion Implant Future Fab Intl. Volume 16, February 03, 2004
As a manufacturer of specialty materials, POCO’s materials research and development teams are constantly working to develop new high-performance materials for specific applications. Development teams use feedback from the field to help identify the characteristics and physical properties that new materials should have to increase equipment performance and improve yields. Input from the field comes from OEM’s as well as end users to develop target materials for specific applications.
Synopsis of Yield Enhancement Chapter of the 2003 ITRS Roadmap Future Fab Intl. Volume 16, February 03, 2004
Yield enhancement (YE) is defined as the process of improving the baseline yield for a given technology node from R&D yield level to mature yield. The definition assumes a functional baseline process for a given process technology and its compatibility with the design of the product being fabricated. The definition emphasizes the chapter focus on the yield ramp portion of the yield learning curve and high mature volume production yield. The YE chapter scope is limited to wafer sort yield. The YE chapter does not address fab line yield, assembly/packaging yield, or final test yield.
Fred Lakhani, International SEMATECH
Views from the Top: Laurent Bosson Future Fab Intl. Volume 16, February 03, 2004
Laurent Bosson graduated in chemistry and physics from the University of Dijon, France. A French national, he began his professional career in 1964. In 1985, he joined what is now STMicroelectronics in Rennes, France. In 1989 he was appointed corporate vice president and director of central manufacturing. In January 1992, he became president and CEO of the company's operation in the Americas. In 1995 he received the mission to set up and start the third eight-inch submicron module of the company in Catania, Sicily, followed by Rousset 200 mm and Singapore 200 mm in 1997. Under his direction the front-end manufacturing organization is presently working on a new 300mm fab called M6 in Catania, Sicily. He has held the position of chairman of the board of the U.S. subsidiary company, STMicroelectronics Inc. since 1996.
Laurent Bosson, STMicroelectronics
Views from the Top: Steve Newberry Future Fab Intl. Volume 16, February 03, 2004
Stephen G. Newberry is President and Chief Operating Officer of Lam Research Corporation, located in Fremont, California. In this position, he is responsible for all product business groups, manufacturing and materials, global sales, global customer support, and corporate administrative and support functions. He joined Lam in 1997. He serves as a board member for Nextest Systems Corporation, the Advisory Board for SEMI North America, and the Advisory Board for Outhink, Inc.
Steve Newberry, Lam Research
Advances in Process Quartzware Cleaning Future Fab Intl. Volume 15, July 11, 2003
This document describes the initial test and evaluation results obtained at International SEMATECH on the QCS 2000TM quartz cleaning system manufactured by QCS Global. Two important considerations in effective quartz cleaning are the chemistry and the application method. Initial testing of the QCS 2000TM’s spray capability to clean quartzware with film deposits of polysilicon and nitride indicates that it cleans more efficiently than immersion-type cleaning equipment.
Robert Groves, International SEMATECH
Alternative Chemistries for Cleaning PECVD Chambers (Applied Materials DxL): C4F8 and C2F6 Based Process Future Fab Intl. Volume 15, July 11, 2003
CVD chambers are cleaned using a plasma etch process that volatilizes residue deposited on the inner surfaces of the process chamber during thin film deposition.
Hubert F. Winzig, Infineon Technologies AG, Uwe Hoeckele, Infineon Technologies AG, Hans Kessler, Infineon Technologies AG, Orest Nowik, Infineon Technologies AG, Kai A. Schreiber, Infineon Technologies AG
Applications of Simulation Modeling at Texas Instruments DMOS5 Wafer Fab Future Fab Intl. Volume 15, July 11, 2003
TI launched a fabwide CT reduction initiative in 2001. As a result, all the modules in DMOS5 identified cycle time reduction projects in their respective modules that target cycle time reduction.
Amit Gupta, Texas Instruments Incorporated, Kishore Potti, Texas Instruments Incorporated
Atomic Layer Deposition for Advanced DRAM Applications Future Fab Intl. Volume 15, July 11, 2003
It is believed that DRAM applications will once again be a major driving force as ALD is being introduced into mainstream semiconductor processing.
M. Gutsche, Infineon Technologies AG, Harald Seidl, Infineon Technologies AG, Thomas Hecht, Infineon Technologies AG, Stephan Kudelka, Infineon Technologies AG, Uwe Schroeder, Infineon Technologies AG
Low Cost of Ownership Tungsten CMP Process Utilizing a Hard Porous Polishing Pad Future Fab Intl. Volume 15, July 11, 2003
The particular applications discussed in this paper are tungsten stud processes used in a seven level aluminum interconnect process.
Tool utilization, pad life and slurry
consumption are all factors that contribute to the cost of polishing a tungsten wafer. In order to improve the cost of ownership of any CMP process, pad life must be extended to its maximum lifetime and slurry consumption must be minimized. This
paper discusses the pad benefits that allow process improvements, that ultimately lead to a lower cost of ownership.
Kyle Hunt, Texas Instruments Incorporated, Ann Hurst, Thomas West
Novel Plasma Enhanced Growth of SiGe in a 200 mm/300 mm Single Wafer Cluster Tool Future Fab Intl. Volume 15, July 11, 2003
The CMOS market is strongly cost driven and based on a steady increase in the density of transistors (Moore’s Law). The SiGe material may help to meet challenges related to the miniaturization, like off-state leakage, gate leakage and the increase in resistance in the MOS transistor[1]. ‘Strained silicon channels’ realized on virtual substrates (VS) increase carrier mobility by 100-200% resulting in an increased saturation current of 20-30% for ‘higher speed’ or the reduction in operating voltage and power consumption. Read more.
Juergen Ramm, Unaxis USA Inc., Hans von Kaenel, EpiSpeed
SECTION 5 INTRODUCTION, VOL 15: Wafer Processing Future Fab Intl. Volume 15, July 11, 2003
In this issue of Future Fab International you will find, once again, the latest news on the most exciting developments in the world of process technology. As device features continue to aggressively scale down,it becomes imperative to control deposition of films to the atomic level. Researchers at Infineon Technologies AG have successfully fabricated sub-100 nm DRAM chips using Atomic Layer Deposition (ALD) of Al2O3 as node dielectric in high aspect ratio
trench capacitors. It is expected that this technique will enable scaling of DRAM capacitors well beyond 100nm features.
Dr. Frank Wen, UMC, Paolo Gargini, Intel Corporation
Application of Plasma Immersion Ion Implantation to Silicon Processing for ULSI Future Fab Intl. Volume 14, February 11, 2003
Plasma immersion ion implantation (PIII) has attracted much attention as a promising and innovative doping technology for processing of silicon (Si) ultra-large-scale-integrated circuits (ULSI). In this article we review typical examples of application areas of PIII, and demonstrate some of the most attractive application areas of PIII for the development of sub-0.15 lm devices, which include sidewall doping of high-aspect ratio deep trenches in Si, ultra-shallow junctions, and multiple-thickness gate oxide process. PIII not only has unique characteristics for each application area, but also improves device performance significantly. Due to its versatility and low cost-of-ownership, PIII is expected to become a vital technique for the development of advanced devices in the near future. In addition, a sputter-etching phenomenon during conformal argon PIII is discussed in this article.
Kilho Lee, Infineon Technologies AG, Helmut H. Tews, Infineon Technologies AG, Brian S. Lee, Infineon Technologies AG, Rajesh Rengarajan, Infineon Technologies AG, Christopher C. Parks, IBM Microelectronics Division, Paul A. Ronsheim, IBM Microelectronics Division, Dan Mocuta, IBM Microelectronics Division, Ronald M. Anderson, IBM Microelectronics Division, Raj Jammy, SEMATECH, James D. Bernstein, Texas Instruments Incorporated, Peter L. Kellerman, Axcelis Technologies
Atomic Layer Deposition for Advanced DRAM Applications Future Fab Intl. Volume 14, February 11, 2003
DRAM technology has been a major driver of innovations in process technology and manufacturing equipment in the microelectronics industry. As the semiconductor industry migrates to ever smaller device geometries, new deposition process technologies will be required to meet the challenges posed by the demand for novel materials, the need to work with ever thinner films, and the necessity to deposit conformal films into structures with increasingly high aspect ratios (AR). Atomic Layer Deposition (ALD) is a very attractive new technology which will open up great opportunities for next generation integrated circuit fabrication. ALD has already demonstrated that it can overcome many of the limitations of current film deposition techniques. ALD has shown unparalleled step coverage performance, superb uniformity and film thickness control, as well as high film quality of dielectric and metal layers. This article reviews the use of ALD for advanced DRAM technology. Infineon is developing ALD films for sub-100nm DRAM capacitor applications and has fabricated industry-first fully functional DRAM chips using ALD Al2O3 as node dielectric in high aspect ratio trench capacitors. The superior performance of ALD technology will enable the scaling of trench DRAM cells well beyond 100nm feature size. It is believed that DRAM applications will once again be a major driving force as ALD is being introduced into mainstream semiconductor processing.
M. Gutsche, Infineon Technologies AG, Harald Seidl, Infineon Technologies AG, Thomas Hecht, Infineon Technologies AG, Stephan Kudelka, Infineon Technologies AG, Uwe Schroeder, Infineon Technologies AG
Challenges Facing 65 nm Particle Metrology and Process Performance to Meet ITRS Requirements Future Fab Intl. Volume 14, February 11, 2003
The ability to solve roadmap challenges is, at least, proportional to our ability to measure them. When process performance is characterized by 65 nm particle measurement, many factors such as the environment, wafer type, metrology, and surface preparation methods play a role in the outcome. To quantify roadblocks and research the solutions, metrology equipment and techniques must not only keep pace, but also outpace the demands of process research and development. In this article, considerations for 65 nm particle metrology and process performance on bare silicon wafers are presented.
Curtis R. Olson, SCP Global Technologies, M. Rao Yalamanchili, SCP Global Technologies, David W. Shortt, KLA-Tencor, Luciano Mule’Stagno, MEMC Electronic Materials, Inc.
Development of Fluoride-Containing Solvent-Based Strippers Future Fab Intl. Volume 14, February 11, 2003
In the early days of the semiconductor industry, mixtures of sulfuric acid and hydrogen peroxide were used to strip photoresist from wet-etched wafers (1). The photoresist removal mechanism involved oxidation of the organic polymer. These mixtures were strong oxidizers and due to safety issues, solvent mixtures that were considerably safer were developed and commercialized. As each new generation of product was developed it retained the benefits of the previous generation, addressed problems, and added new capabilities. The semiconductor stripper and cleaner market is now dominated by a few classes of solvent-based products; aminebased, amide-based, and fluoridecontaining solvent-based strippers.
Darryl Peters, Confluense, LLC, Les Molnar, Ashland Specialty Chemical Company, Robert Rovito, Ashland Specialty Chemical Company
Downstream Solutions for LPCVD Thermal TEOS Silicon Dioxide Processes Future Fab Intl. Volume 14, February 11, 2003
This document describes the results obtained on International SEMATECH’s SVG 7000 Vertical LPCVD TEOS double wall configuration furnace. After installation of an HPS Virtual Wall™ an improvement in MTBF was realized along with a reduction in MTTR. The effectiveness of the virtual wall permitted operation of the furnace until EOL of the process quartzware at 75.7 microns.
Robert Groves, International SEMATECH, Paul Dozoretz, MKS Instruments
Low Cost of Ownership Tungsten CMP Process Utilizing A Hard Porous Polishing Pad Future Fab Intl. Volume 14, February 11, 2003
The selection of CMP polishing pads has historically been limited to the few types of solid polyurethane pad types available on the market. This selection of pads did not allow for the much-needed flexibility required to reduce the cost of the tungsten CMP process. A new hard porous pad has been tested and implemented at Texas Instruments, Inc. that allows significantly lower cost of ownership for the tungsten CMP process. The particular applications discussed in this paper are tungsten stud processes used in a seven level aluminum interconnect process.Tool utilization, pad life, and slurry consumption are all factors that contribute to the cost of polishing a tungsten wafer. In order to improve the cost of ownership of any CMP process, pad life must be extended to its maximum lifetime and slurry consumption must be minimized. This paper discusses the pad benefits that allow process improvements, which ultimately lead to a lower cost of ownership.
Kyle Hunt, Texas Instruments Incorporated, William. R. Morrison, Texas Instruments Incorporated, Ann Hurst, Thomas West
Benefits and Applications of Single Wafer Immersion Wet Processing Future Fab Intl. Volume 13, July 08, 2002
 The motivations for shifting from batch to
single wafer processing are explored in this
paper, with a particular emphasis on the
challenges associated with accomplishing
wet process steps such as surface
preparation and etching in a single wafer
platform. While the number of wet process
steps has more than doubled over the last
ten years with even higher performance
expectations, the search for a suitable single
wafer replacement for the traditional batch
immersion wet benches has not been
resolved.
John J Rosato, SCP Global Technologies, Jermome A Imonigie, SCP Global Technologies, M. Rao Yalamanchili, SCP Global Technologies, Eric Hansen, SCP Global Technologies
Characterization and Control of Cu Electroplating Chemistries for On-chip Metallization Future Fab Intl. Volume 13, July 08, 2002
Electroplated Cu is currently used by various
major semiconductor manufacturers as an
interconnect material due to its lower
electrical resistance and better
electromigration characteristics over
conventional Al interconnects. This paper
describes characterization and control of Cu
electroplating chemistries in the
semiconductor-manufacturing environment.
Valery M Dubin, Intel Corporation, Roger R Brewer, Intel Corporation, Harsono Simka, Intel Corporation, Sadasivan Shankar, Intel Corporation
Cost Reduction Challenges in CVD Chamber Cleaning: Strategies to Reduce Gas Costs Future Fab Intl. Volume 13, July 08, 2002
CVD chamber cleaning gases contribute
significantly to the overall material costs in
semiconductor manufacturing. Besides the
specifications, the consumption of CVD
clean gases is the most important leverage
to reduce gas costs as part of a total cost of
ownership approach considering clean
performance and PFC* emissions as
additional key parameters.
In this context, the utilization of the
clean gas in the plasma is a crucial factor
selecting better chemistries for CVD
chamber cleaning.
Oliver F. Schedlbauer, Infineon Technologies AG, Hubert F. Winzig, Infineon Technologies AG
Mitigating Equipment Supplier Risks for the 300mm Transition Future Fab Intl. Volume 13, July 08, 2002
The 300mm retooling of the semiconductor
industry is considered by many the largest the
industrial world has ever seen. The magnitude
of the transition forced the whole industry to
reevaluate how to manage a wafer size
transition. One of the biggest challenges was
ensuring that the 300mm equipment
suppliers could provide manufacturing-ready
equipment to support a quick transition.
Previous wafer generation conversions saw
initial equipment offerings that were not
mature, with many beta tools inserted in early
manufacturing sites.
Robert E. Bruck, Intel Corporation
The Motorola Coin-Stack/Air Cushion Wafer Packaging System Future Fab Intl. Volume 13, July 08, 2002
“All the manufacturing and testing quality
control in the world is meaningless if the
product gets broken during transit to the
end-user.”
Bill Duncan,
Motorola Advanced Technology
Center-Transport Packaging Solutions
Bill Duncan, Motorola , Walter M Skurda, Motorola , Neil Ross, Freescale Semiconductor, Barry Watson, Motorola
Advanced 300mm Wafer Surface Preparation Methods for Sub-130nm Device Processing Future Fab Intl. Volume 12, February 02, 2002
With the gate oxide thickness values approaching less than 20 Å for sub-130nm design rules, surface preparation requiments are becoming more critical than ever. Surface preparation requirements outlined by ITRS for current and future device technology nodes for particles, watermarks, and etch uniformity are very stringent and difficult to meet with traditional surface preparation processes[1].
Stephen J. Buffat, Lockheed Martin Corporation, Matthew S. Lucey, SCP Global Technologies, M. Rao Yalamanchili, SCP Global Technologies
Development and Implementation of 300mm Cu CMP Manufacturing Systems Future Fab Intl. Volume 12, February 02, 2002
Advanced interconnect technologies using copper as the interconnect material of choice along with a variety of dielectric materials were also planned for rapid implementation on 300mm wafers. In fact, Cu CMP has emerged as a critical back-end-of-the-line (BEOL) processing step for advanced interconnect technologies and has posed a serious challenge for 300mm production. In the 300mm Cu process flow, given the increased cost of ownership, there exists a need for Cu CMP process that meets the low topography requirements of multi-level damascene structures while meeting IC device performance requirements.
R. Tiwari, Texas Instruments Incorporated, M. Soucek, Texas Instruments Incorporated, Joel Strupp, Texas Instruments Incorporated
Interconnect Challenges and Strategic Solutions Future Fab Intl. Volume 12, February 02, 2002
To continue to meet the industry requirements of scaling to smaller dimensions and to realize performance improvement, technologies are forced to include Cu interconnect and dielectrics with low dielectric constant[1].
Navjot Chhambra, International SEMATECH, Ken Monnig, International SEMATECH, Roderick Augar, International SEMATECH, Dr Jeffrey T. Wetzel, SVTC Technologies, LLC, Freddie Hampton , International SEMATECH
STI Planarization Using Fixed Abrasive Technology Future Fab Intl. Volume 12, February 02, 2002
Chemical mechanical polishing (CMP) is the planarization technique of choice for shallow trench isolation (STI). Conventional CMP processes utilize polyurethane polishing pad and liquid chemical slurry containing abrasive particles. Silica and ceria abrasives have been used for STI planarization.
Laertis Economikos, IBM Microelectronics Division, Fen-Fen Jamin, IBM Microelectronics Division, Alexander Simpson, Infineon Technologies AG, Adam Ticknor, IBM Microelectronics Division
300mm Tool and Process Development for a Dual In-Laid Copper Interconnect Future Fab Intl. Volume 11, June 29, 2001
Motorola and Infineon, the first to become heavily engaged in the 300mm arena, have been shown to be very successful in developing a 300mm tool set to produce a 64M DRAM, a product that has been qualified and sold out of the 300mm pilot line. This technology uses an aluminum back end of line (BEOL) interconnect scheme. Motorola’s leading edge technologies, however, have copper at the BEOL. To satisfy these needs, an independent development effort was launched to focus on a tool set for processing a Dual In-Laid copper technology. The objective was therefore to develop a 300mm tool set, with the capability of creating a Dual In-Laid copper interconnect for a leading edge CMOS logic baseline technology. In addition, it was required that each unit process step be demonstrated on tools manufactured by at least two or more equipment suppliers. The process tools were housed at the supplier sites, where wafers were moved through as the technology flow dictated.
Freddie Hampton, Motorola , Douglas Keenan, Motorola
A New Design for Quartz Tube Cleaning Future Fab Intl. Volume 11, June 29, 2001
Furnace process chambers used in semiconductor industries (thermal processes APCVD, LPCVD) require preventive maintenance (cleaning). Essentially, after a certain number of processed wafers (oxidisation/ deposition), the process chamber must be removed from the furnace to be cleaned. The purpose of cleaning is the removal of deposits and residuals that are on the process environment walls (process chamber).
Fabio Somboli, Segibo, Raffaele Ninni, STMicroelectronics
Integration Challenges of the Low-k Roadmap Future Fab Intl. Volume 11, June 29, 2001
Michael E Mills, The Dow Chemical Company, Mark McClear, The Dow Chemical Company
Observations of Pattern-Dependent Plasma Charging and Polymer Deposition During Deep Trench Dry Etch Future Fab Intl. Volume 11, June 29, 2001
Richard Wise, IBM Microelectronics Division, Siddhartha Panda, IBM Microelectronics Division, Swami Mathad, Infineon Technologies AG, Rajiv Ranade, IBM
Optimized Surface Preparation Technologies for Improved Gate Oxide Integrity in Thin Nitrided-Oxides Future Fab Intl. Volume 11, June 29, 2001
Debra R Acock, ZiLOG , John A Smythe, ZiLOG , John J Rosato, SCP Global Technologies
SOG Annealing Applications Using a Hot Plate-based Mini-batch System Future Fab Intl. Volume 11, June 29, 2001
Jiro Yamamoto, NEC Hiroshima , Woo Sik Yoo, WaferMasters , Takashi Fukada, WaferMasters
300mm Wafer Carrier Interoperability on Wafer Processing Equipment Future Fab Intl. Volume 10, July 01, 2001
300mm wafer fabs will have an unprecedented increase in automation and focus on per-chip cost and per-factory output. There has been a steady increase in the automation of wafer fabs for the past two decades. At 300mm the goal is finally to have 100% automation of the work in process wafer transport. Wafer carriers are a focus of this automation. The automated material handling systems move the wafers from process tool to process tool, with the wafers contained in and protected by a wafer carrier. Each wafer carrier in the fab is expected to be interoperable with every process tool load port. The wafer carrier has become a critical component of the fab, critical to overall 300mm manufacturing success.
Bob Komma, Entegris, Inc. , Tracy Nielberg, Entegris, Inc.
Chemical-Mechanical Polishing of Copper for Advanced Semiconductor Device Fabrication Future Fab Intl. Volume 10, July 01, 2001
C Yu, Cabot Microelectronics Corporation
E79: Standards, Signals and the Internet. Project iPlus: Using the E79 Standard to Design a Future Fab Intl. Volume 10, July 01, 2001
Peter Gaboury, STMicroelectronics , Thomas Vonderstrass, Industrial Design Corporation
Improved Implant System Performance using Pyrolytic Infiltrated Graphite - POCO Future Fab Intl. Volume 10, July 01, 2001
Integration and Reliability of 0.18μm Manufacturable Interconnects Using Low K Future Fab Intl. Volume 10, July 01, 2001
WW Lee, Taiwan Semiconductor Manufacturing Corporation
Motorola Silicon Wafer Packaging Evolution Future Fab Intl. Volume 10, July 01, 2001
Bill Duncan, Motorola , Chad Thompson, UPS Professional Services, Neil Ross, Freescale Semiconductor, Walter M Skurda, Motorola
Surface Characterization of Light Organic Removal in Ozone Processes Future Fab Intl. Volume 10, July 01, 2001
Akshey Sehgal, SCP Global Technologies, M. Rao Yalamanchili, SCP Global Technologies, John J Rosato, SCP Global Technologies
300mm Silicon Driven by Total Cost Minimization Future Fab Intl. Volume 9, January 07, 2000
Despite the frequent design shrinks and all the equipment and process innovation that comes with them, the added complexity of new chip generations enlarges the size of a chip. To stay on Moore’s law is only possible by enhancing the batch size of chips per wafer, or in other words to convert to the next diameter. It seems to happen at about every nine years. Global industry-wide consensus about the size of the next wafer is as important as the right timing.
Peter Hahn, Wacker Siltronic, Hermann Fußstetter, Wacker Siltronic
IPA Vapor Drying Technology to Meet Surface Preparation Challenges for Sub - 0.18 μm Design Rules Future Fab Intl. Volume 9, January 07, 2000
M. Rao Yalamanchili, SCP Global Technologies, John J Rosato, SCP Global Technologies
Polysilicon Planarization and Plug Recess Etching in a Decoupled Plasma Source Chamber Using Two Endpoint Techniques Future Fab Intl. Volume 9, January 07, 2000
George Kaplita, IBM
Strategies for Small to Medium Scale Fabs Future Fab Intl. Volume 9, January 07, 2000
Murty Polavarapu, Lockheed Martin Space Electronics & Communications, Peter Spreen, Lockheed Martin Space Electronics & Communications
The Inception of Chemical-Mechanical Polishing for Device Applications at IBM Future Fab Intl. Volume 9, January 07, 2000
Klaus Beyer, IBM
Wafer Bumping Technology: Gateway to Higher End Applications Future Fab Intl. Volume 9, January 07, 2000
Alex Papalexis, Fujitsu Corporation
Critical Cleaning Challenges for Copper / Low-k Interconnect Systems Future Fab Intl. Volume 8, July 01, 2000
John J Rosato, SCP Global Technologies
Integration Challenges of Low-k Materials Future Fab Intl. Volume 8, July 01, 2000
WW Lee, Taiwan Semiconductor Manufacturing Corporation, Steve Russell, Texas Instruments Incorporated
Low-k Dielectric Materials for Advanced Interconnect Applications Future Fab Intl. Volume 8, July 01, 2000
Todd Ryan, SEMATECH, Robert Fox III, SEMATECH
Photostabilization Optimization of N-Well and P-Well Resist Processes Future Fab Intl. Volume 8, July 01, 2000
Dave Harris, LSI Logic Corporation, Donna Whiteside, Eaton Corporation - SEO, Fusion Systems Division, Robert Mohondro, Tevet Process Control Technologies
The Effect of Peripheral Support Equipment on Overall Fab Performance Future Fab Intl. Volume 8, July 01, 2000
David Cawse, Mitel Semiconductors
Tool and Facility Considerations for Small to Medium Scale Fabs Future Fab Intl. Volume 8, July 01, 2000
Murty Polavarapu, Lockheed Martin Space Electronics & Communications, Wade Rouffa, Lockheed Martin Space Electronics & Communications
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