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 Section 7 Introduction: Metrology Failure Analysis Future Fab Intl. Volume 23, July 09, 2007
Some time ago, some folks with significant industry experience at large suppliers stated that the adoption of sensor-based process control, and the survival of small suppliers of sensor-based equipment, required a successful business plan. About 10 years later, AEC-APC has become a key enabler for improved yield and process efficiency.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany, Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden
Advanced X-ray based thin-film metrology from Jordan Valley. For resolution, nothing else measures up. Future Fab Intl. Volume 23, July 09, 2007
You wouldn’t settle for poor resolution at home.
Why allow it in your fab?
AMS Understands That Metrology Is Not Just About Measurement Future Fab Intl. Volume 23, July 09, 2007
Today the semiconductor industry is
changing almost as fast as the technologies
it serves. Gone are the days of
lengthy product cycles and straightforward
metrology solutions that would fit a
device manufacturing process – from pilot
to production – over an extended period
of time.
Impact of Wafer-Level 3D Stacking on the Yield of ICs Future Fab Intl. Volume 23, July 09, 2007
Semiconductor manufacturing is all
about yield. Today 3D-ICs are a hot topic,
but manufacturers need to know how 3D
will impact their yield percentages. This
chapter seeks to investigate the issue
from several angles.
Robert Patti, Tezzaron Semiconductor
Infrared Metrology of 3D Structures Future Fab Intl. Volume 23, July 09, 2007
Driven by the continued demand for
increased functionality in integrated circuits,
the trend toward ever-higher levels
of integration has resulted in the use of
increasingly three-dimensional structures
in order to get more function out of a
given area.
Michael Gostein, Advanced Metrology Systems, Alex A. Maznev, Advanced Metrology Systems
Think of us as custom metrology tailors. Metaphorically speaking. Future Fab Intl. Volume 23, July 09, 2007
If you think it’s hard to find a metrology system that fits well today,
you’re not alone. The semiconductor industry is changing almost
as fast as the technologies it serves.
Breakthrough of X-ray Techniques in Analytics and Metrology Future Fab Intl. Volume 22, January 09, 2007
In this paper, we would like to demonstrate
the high potential of the X-ray techniques
for analytics and metrology in the
semiconductor industry, and that we are
living in a decade which is characterized
by a breakthrough in the industrial application
of these techniques. We will
describe the implementation of these
techniques for industrial applications,
particularly advanced process development
and process monitoring, and we
will provide an outlook about the bright
future of these techniques.
Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden, Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany
Combining Confocal Raman and Atomic Force Microscopy for High-Resolution Stress Measurements in Semiconductors Future Fab Intl. Volume 21, July 01, 2006
In this work, Raman spectral imaging
was used to investigate the local stress
fields in semiconductors. Raman spectroscopy
is a powerful, nondestructive
analysis technique that delivers detailed
chemical information about the molecules
involved in the scattering process. By analyzing
the peak position of the Raman lines
with high precision, even stress measurements
in materials, like semiconductors,
are possible.
In Raman spectral imaging mode, a
complete Raman spectrum is recorded at
every confocal imaging point with integration
times below 100 ms, while the sample
is scanned in XY-direction. The automated
evaluation of spectral features (sum, peak
position, width, etc.) from the large number
of recorded spectra (typically 10,000 to
100,000 spectra) produces chemical
images of the analyzed material, or in this
case, the stress distribution.
Olaf Hollricher, WITec GmbH, Wolfram Ibach, WITec GmbH, Andrea Jauss, WITec GmbH, Ute Schmidt, WITec GmbH
INTRODUCTION SECTION 8 - METROLOGY/FAILURE ANALYSIS Future Fab Intl. Volume 21, July 01, 2006
The Metrology/Analysis section of Future
Fab International concentrates on analytical
techniques that should be considered in future
metrology strategies for wafer-level manufacturing
of logic and memory products. Increase
of product performance and continuous cost
reduction per function are the driving forces
for scaling the MOS transistor gate length of
microprocessors and the density of capacitors
for DRAMs. In both cases, the traditional scaling
of the device structures alone will not be
sufficient anymore to meet future performance
goals. In addition, new materials and
“nonclassical” devices are introduced or under
development, which result in new challenges
to the device metrology. Major challenges to
Front-End-Of-Line analytics and metrology
are today:
Christian Boit, Berlin University of Technology, Germany, Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden
INTRODUCTION SECTION 8 - METROLOGY/FAILURE ANALYSIS Future Fab Intl. Volume 21, July 01, 2006
Often, inventions are met with great expectations.
The advantages of the invention are
described in terms of meeting nearer-term
requirements, while the true incubation time
the technology including its acceptance is more
long term. Despite this, advocates often demonstrate
the usefulness of the new technology
with near-term examples and miss the opportunity
to demonstrate whether or not a technology
can meet the needs at first use and show
extendibility. Herein lies a conundrum. The
most useful evaluation of a new measurement
technology is on materials or structures that
best represent the variety of situations in which
the equipment will be used.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany
Model-Based Infrared Reflectometry: In-Line Applications for DRAM Manufacturing Future Fab Intl. Volume 21, July 01, 2006
The shrinking of integrated circuit
devices is bringing an increased demand
for in-line automated metrologies for structural
control of vertical features. For example,
vertical structure control is now important
in advanced deep-trench DRAM.
Model-Based Infrared Reflectometry
(MBIR) is a new technology that offers
compelling advantages for in-line monitoring
of such DRAM structures, in addition to
other applications. This article will discuss
several aspects of in-line monitoring at a
deep-trench DRAM fab, with specific
examples related to yield issues. Tool performance
and future applications will be
highlighted.
Inotera Memories / Qimonda
SECTION 8 – INTRODUCTION: METROLOGY/FAILURE ANALYSIS Future Fab Intl. Volume 20, January 07, 2006
The 2005 Metrology Roadmap was
released in December along with the entire
International Technology Roadmap for
Semiconductors. Once again, measurement
specialists from all the semiconductor-producing
regions provided key assessments of the
status of existing measurement technology and
projected future requirements and potential
solutions. The ITRS projects the year of volume
production for the first two companies manufacturing
qualified chips. A qualified chip is one
approved by its customer. One of the frequently
forgotten needs is for early versions of a
process or production worthy measurement
system for the next technology generation three
years beforehand. Process tool development
occurs a number of years before the Alpha tool
is sent to an IC manufacturer. Some form of
metrology must be ready to support the development
of new materials, structures and
process tools. The moral of this story is that
alpha, beta and production tools are needed
long before the date associated with a technology
node. Therefore, research and development
for the 45/32nm node metrology needs should
be well underway in 2006. Research into measurement methods for the 22nm node should be
(or has already been) initiated. As has been frequently
stated, the biggest inhibition for metrology
research is the availability of materials and
structures for future technology generations.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany
SECTION 8 – INTRODUCTION: METROLOGY/FAILURE ANALYSIS Future Fab Intl. Volume 20, January 07, 2006
The Metrology/Failure Analysis section of
Future Fab International usually concentrates
on analytical techniques for metrology and yield
enhancement. This issue is not an exception,
and we will introduce the contributions later.
Christian Boit, Berlin University of Technology, Germany
Strain Measurement by Transmission Electron Microscopy Future Fab Intl. Volume 20, January 07, 2006
Strain engineering has become an
important tool to allow the semiconductor
industry to meet roadmap requirements
for device performance in the face of limits
to device scaling. Strain is used to affect
the electronic band structure to improve
carrier mobility in the channel region of
MOSFET devices. The development of
strain-engineered devices requires the
ability to measure local strains in the critical
channel region of fully processed
devices. Currently, only transmission electron
microscopy (TEM) has proven capable
of measuring such buried strains at the
required spatial resolutions. This article
will review and assess several TEM methods
of local strain measurement.
Brendan Foran, ATDF , Mark H. Clark, ATDF , Guoda Lian, Texas Instruments
The FABLAB Concept: Future Challenges to Analytics and Metrology in the Semiconductor Industry Future Fab Intl. Volume 20, January 07, 2006
In the not-too-distant future, the
extraordinarily minute scale of device features
will severely test the existing analysis
and metrology techniques currently in
use. To support the manufacturing processes
needed for next-generation technology
cycles, nanoscale materials analysis
and metrology for micro- and nanoelectronic
devices have to be established.
In a new approach aptly named “FABLAB”
these issues will be characterized by the
amalgamation of exploration into new
microscopy, scattering and spectroscopy
techniques in the offline laboratory with
the implementation of these techniques
for the purpose of nondestructive inline
metrology. This paper outlines the concept
and its implications for the changing
face of the industry’s needs as we step
deeper into the nano-age.
Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden, Ulrich Mantz, Infineon Technologies AG, Peter Kücher, Fraunhofer Center of Nanoelectronic Technologies
Understanding Imaging of Silicon and Germanium Nanowires Through Simulation Future Fab Intl. Volume 20, January 07, 2006
Research, development and manufacturing
of nanotechnology, especially
nanoelectronic technology, requires the
ability to image at near atomic dimensions.
In many circumstances, transmission
electron microscopy (TEM) can now
provide the necessary imaging. The
recent introduction of aberration-corrected
lens technology has extended
spatial resolution to less than 0.1nm.
High-resolution TEM images and electron
diffraction patterns of nanowires
show phenomena not present in images
of bulk materials. In this paper we discuss
how simulating these images provides
new insight into the interpretation
of these images. Simulated electron
diffraction patterns point toward the
possibility of determining the surface
morphology of nanowires. This understanding
will provide the methodology
necessary for imaging nanoelectronic
devices such as FINFETs.
T. Hanrath, University of Texas at Austin, D.C. Lee, University of Texas at Austin, B.A. Korgel, University of Texas at Austin, Alexander Thesen, Carl Zeiss SMT-Nano Technology, Marco Matijevic, Carl Zeiss SMT-Nano Technology, Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany
A Review of Scatterometry for Three-Dimensional Semiconductor Feature Analysis Future Fab Intl. Volume 19, June 28, 2005
The continuing demand for higher-frequency
microprocessors and larger-capacity
memory arrays has led to decreasing
device dimensions and smaller process
control windows. To maintain these tighter
specifications, accurate, high-precision
metrology is required to achieve an acceptable
precision-to-tolerance ratio. Furthermore,
the need to detect, identify and
measure changes in the feature profile and
film stack, including reflectivity, layer thickness
and sidewall angle, is becoming critical
for sub-90 nm technology for both 2-D
and 3-D structures. Measuring these
changes as well as detecting subtle phenomena
such as line-rounding, t-topping
and resist footing has become as important
as – or even more important than - the traditional
critical dimension measurement.
John Allgair, ISMI (AMD assignee), Austin, TX, Benjamin Bunday, International SEMATECH Manufacturing Initiative
Introduction: Metrology and Failure Analysis Future Fab Intl. Volume 19, June 28, 2005
The Metrology/Failure Analysis section of this Future Fab International edition
concentrates on process control needs and respective techniques for future wafer-level
processing. Two papers focus on advanced metrology which is needed for process
control of device structures with smaller feature sizes, new materials and new
device architectures: scatterometry and model-based infrared (IR) spectroscopy.
The third paper on synchrotron-radiation transmission X-ray microscopy (XTM)
demonstrates the potential of this sophisticated analytical technique for Cu/low-k
stack characterization, including real-time imaging of reliability-limiting
processes in on-chip interconnects.
Christian Boit, Berlin University of Technology, Germany, Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden
Introduction: Metrology and Failure Analysis Future Fab Intl. Volume 19, June 28, 2005
Back in the July 1997 issue of Future Fab
International, Bob McDonald and I published an
article on “The At-Line Characterization
Laboratory of the ’90s.” After the ITRS and
Semicon Europa meetings, I visited Ehrenfried
Zschech at AMD in Dresden. AMD is continuing
this trend with what might be called the FABLAB
of the early 2000s. AMD’s FABLAB has 300 mm
capable characterization equipment, software to
aid in navigation to specific locations on the
wafer, and advanced microscopy. This lab
serves as a shining example of how important it
is to tie the LAB to the FAB. Laurens Kwakman
of Philips gave a great presentation on the 300
mm Laboratory of the Crolles2 Alliance at the
2005 Characterization and Metrology for ULSI
Technology Conference. Sematech once again
cosponsored this conference.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany
Model-Based Infrared Spectroscopy: New Opportunities for In-Line Process Control Future Fab Intl. Volume 19, June 28, 2005
Improved chip performance and productivity
are main drivers for next-generation
semiconductor manufacturing technologies.
Looking at the International Technology
Roadmap for Semiconductors, future
technologies do not include only smaller
feature sizes, there is also a significant number
of innovations coming up to make
future devices work. Two main areas, where
significant effort has already been spent in
research and development, are new materials,
including deposition techniques as well
as structures and devices, exhibiting vertical
features. So far, process learning in an early
phase of research and development is
mainly based on destructive techniques or
methods, which are available in labs.
However, shrinking process windows and
the need of improved control of process
variations across the wafer, from wafer to
wafer, and from lot to lot directly on patterned
wafers will fuel the demand for new,
fully automated in-line measurement methods
for both structural control of vertical
features and material characterization.
Even in an early development phase, nondestructive,
full wafer measurements help
speed up process learning significantly. We
already see some methods moving from a
laboratory environment into the clean
room, but many future metrology challenges
remain unsolved so far. One method,
which recently became available in a production
worthy in-line configuration, is
model-based infrared spectroscopy (MBIR).
This method can be applied for control of
vertical structures and material characterization
on product wafers. In this paper, we
will show examples for the use and implementation
of in-line MBIR and give an outlook
on further potential applications, which
still need to be explored to their full extent.
Ulrich Mantz, Infineon Technologies AG, Alexander Kasic, Qimonda
X-ray Microscopy: A Powerful Tool for Electromigration Studies in Modern ICs Future Fab Intl. Volume 19, June 28, 2005
For leading-edge microelectronic products
like microprocessors, each new technology
node that comes along with
smaller dimensions of on-chip interconnects,
advanced backend-of-line (BEoL)
manufacturing process steps and/or
changed combinations of thin film materials
is leading to new reliability challenges:
different microstructure of the
metal interconnects, other types of interfaces
and as yet unknown degradation
phenomena. Electromigration, stressinduced
phenomena and – in case of lowk
materials – mechanical weakness are
reliability concerns for inlaid copper
interconnects.[1,2]
G. Schneider, BESSY m.b.H., S. Rudolph, BESSY m.b.H., A.M. Meyer, AMD, Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden, P. Guttmann, Institut fur Rontgenphysik c/o BESSY
Control of Selective Epitaxial Growth In Semiconductor Manufacturing Future Fab Intl. Volume 18, January 12, 2005
Selective epitaxial growth (SEG) is
one of the new process candidates to
provide a solution for the production of
high-performance devices at the sub-65-
nm node when substantial integration
problems are encountered. However,
there are challenges in monitoring this
kind of new process. In this study, we’ve
demonstrated that applying suitable
metrology can result in good quantitative
methods for selectivity and epitaxy
quality monitor. Moreover, we can also
observe the precise information of the
incoming samples, which is critical to the
epitaxial growth.
Ellen Cheng, UMC, Jay Chen, KLA-Tencor, Chiung-Shu Wang, KLA-Tencor
Failure Analysis And Defect Review For The 45 nm Node Using Extended Accuracy Of The CrossBeam Technology Future Fab Intl. Volume 18, January 12, 2005
As we look forward to the 65 nm and 45
nm technology nodes, challenges arises in
virtually every aspect of the semiconductor
industry. The push to smaller dimensions
puts demands on lithography and mask
making, as well as etching processes. The
push for new materials to increased
frequencies creates challenges with
deposition, patterning, integration and
inspection, as well as packaging. Fab
automation continues to be important, not
only in terms of optimizing yield and fab
efficiency, but also in terms of supply chain
management. Equipment and materials
suppliers, and their own suppliers of
components and subsystems, are developing
tools to meet these challenges.
Peter Gnauck, Carl Zeiss SMT-Nano Technology
SECTION 8: INTRODUCTION Future Fab Intl. Volume 18, January 12, 2005
Many aspects of metrology require modeling. Almost every measurement
requires a model that calculates the value of an observable from the measurement
signal. For example, film thickness is calculated from the value of the
ellipsometric parameters y and D using an optical model of the dielectric function.
There is another “equipment model” that takes the observed signal and
calculates y and D. All metrology uses these types of models. In this editorial,
we discuss another type of modeling that allows us to determine critical
information using the measured value of a related parameter. Similar concepts
are used by the advanced equipment and process control communities.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany, Christian Boit, Berlin University of Technology, Germany, Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden
Metrology Challenges for Ultra-Low-k Dielectrics for the 45 nm Node Future Fab Intl. Volume 17, June 21, 2004
The integration of low-k dielectrics into
Cu interconnects has proved to be a
daunting technological challenge that has
been delayed for several technology nodes
since the first announcement in the
Technology Roadmap in 1994.[1] The delay
can be attributed to the difficulties in
integrating the low-k dielectrics into the Cu
dual-damascene structure, which requires
developments of new materials, processes,
and structures.
Paul S. Ho, University of Texas at Austin
Section 8 Introduction, Vol. 17: Metrology Analysis Future Fab Intl. Volume 17, June 21, 2004
The dream of microscopy is providing an
atomic map in three dimensions. Recently both
transmission electron microscopy and local
electrode atom probe have moved this dream closer
to reality. The drive for an atom-by-atom view of a material comes from the world of nanoelectronics as well as the other areas of nanotechnology. A significant part of this dream includes chemical information to accompany the elemental maps.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany
Section 8 Introduction, Vol. 17: Metrology Analysis Future Fab Intl. Volume 17, June 21, 2004
Performance increase in leading-edge
microelectronic products has been achieved in
the past mostly by faster transistors, as a result of downscaling of device features, and by a more dense packing of transistors on a chip. On the other hand, continuous shrinking of dimensions
increases signal delays caused by on-chip
interconnect wiring, which may soon seriously
limit the performance of integrated circuits.
Prof. Dr. Christian Boit, Infineon Technologies AG, Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden
Structure Characterization of Porous Interlevel Dielectric Films Future Fab Intl. Volume 17, June 21, 2004
To extend the dielectric constant of
interlevel dielectrics below a value of ~2.6
seen in today’s IC chips, porous low-k
material has been evaluated as a viable
candidate by industries. In this paper, the
current status and the future need in
metrologies for characterizing porous
structure including porosity and pore size
distribution are discussed.
Wen-li Wu, National Institute of Standards and Technology, Christopher L. Soles, National Institute of Standards and Technology, Eric K. Lin, National Institute of Standards and Technology
Vibrational Spectroscopy of Ultra-Low-k Dielectric Materials Future Fab Intl. Volume 17, June 21, 2004
FTIR and Raman spectroscopy are
complementary vibrational spectroscopy
techniques that help elucidate the molecular
bonding and molecular structure in low-k
materials. Raman spectra arise from inelastic
scattering of the incident energy from a laser
source, as a function of molecular vibrational
energy. FTIR spectra arise from absorption of
polychromatic radiation at specific energies of
molecular group vibrations. Due to different
selection rules, the two techniques are
sensitive to different types of bonding and
molecular geometries.
Nancy Klymko, IBM Microelectronics Division
2003 ITRS Metrology Roadmap Future Fab Intl. Volume 16, February 03, 2004
The rapid shrinking of feature size and introduction of new materials continue to challenge metrology. The 2003 Metrology Roadmap describes the metrology requirements over the next 15 years for traditional CMOS and for emerging devices. As in previous years, the roadmap is divided into sections that reflect process area needs and cross-cut metrology needs. This year the sections are: measurements for processes facing statistical limits and physical structures reaching atomic dimensions; microscopy; lithography metrology; front-end processes metrology; interconnect metrology; materials and contamination characterization; integrated metrology; reference measurement systems; reference materials; and characterization and metrology for emerging devices. In this article, we provide an overview of the 2003 Metrology Roadmap.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany
Applications of Raman Spectroscopy in Semiconductor Processing Future Fab Intl. Volume 16, February 03, 2004
Mechanical stress is an important reliability issue for the processing of ICs or MEMS and packaging of chips. We describe a nondestructive optical technique that can be used to monitor this stress: micro-Raman spectroscopy (μRS). It can be used to perform high-resolution stress-mapping at different levels: in IC devices, chips, wafers, and packaged chips; and during different processing steps: after shallow- or deep- trench isolation; in strained channels; after silicidation; etc.
Ingrid De Wolf, IMEC
Characterization of Lithography Performance in High-End Semiconductor Manufacturing with Electrical Linewidth Measurements Future Fab Intl. Volume 16, February 03, 2004
This article presents a production-worthy method for the characterization of high-end lithography-exposure tools in semiconductor manufacturing. The principle of the method is based on the electrical linewidth measurement (ELM) technique of conducting layers such as doped poly Si. As the measurement time of ELM is orders of magnitude smaller than for CD-SEM, the method allows the collection of huge amounts of data for extensive statistical analysis. This enables the collection of statistically relevant data for applications like the characterization of the complete image field of lithographic exposure tools. The results of the experiments confirm the method as a powerful tool for the characterization of lithographic exposure tools.
P. Fernandez-Martinez, Infineon Technologies AG, T. Marschner, Infineon Technologies AG, C. Fulber, Infineon Technologies AG, J.W. Bartha, Infineon Technologies AG
SECTION 7 INTRODUCTION, VOL 16: Metrology/Failure Analysis Future Fab Intl. Volume 16, February 03, 2004
The Metrology/Analysis section of this edition of Future Fab International concentrates on process control techniques that should be considered in future metrology strategies for wafer manufacturing. Our first presentation is a fast electrical characterization technique for linewidth of conducting materials that does not suffer from imaging problems. The second one is an analysis technique well known for stress measurements in solids, Raman spectroscopy, here applied to small areas. Mechanical stress is more and more introduced purposely in devices to improve electrical properties such as carrier mobility in strained silicon. For those and further technologies, micro-Raman is a convincing approach with a strong process control potential.
Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden, Prof. Dr. Christian Boit, Infineon Technologies AG
SECTION 7 INTRODUCTION, VOL 16: Understanding Nano-Technology Manager Metrology - Yield Management Program, International SeMaTech Future Fab Intl. Volume 16, February 03, 2004
Once again, the editorial for the Metrology section covers the topic of nano-technology. In this editorial, the topic “Understanding Nano-Technology Metrics” leads us into a discussion about the need for comparing nano-technology-based transistors such as nanowire and carbon-nanotube transistors to the first sub-10 nm CMOS nanotransistors. Nonclassical P-MOS transistors with 6 nm gate lengths have been fabricated on very thin-bodied SOI (silicon on insulator) substrates. These transistors are truly nano-technology. It is useful and important to relate their electrical characteristics to the characteristics of the nanowire and nanotube transistors. Jim Hutchby and co-workers at SRC have a developed an important and interesting discussion of the requirements for emerging technology to move into the world of micro-electronics. The 2003 International Technology Roadmap for Semiconductors contains an extended discussion that is critical reading for those interested in nano-technology.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany
Taking Control of the Copper Process at 65 nm Future Fab Intl. Volume 16, February 03, 2004
The move from aluminum to copper (Cu) interconnects has been driven primarily by the desire for better device performance.
However, the transition to Cu created a number of unexpected challenges that slowed the rate of Cu adoption at the
130 nm node and stalled efforts to integrate low-k dielectrics into the interconnect. The transition to the 90 and 65 nm
nodes has introduced an entirely new set of challenges. This article explores each of these issues in detail and describes the
best-known metrology methods currently available to help IC manufacturers bring the copper process under control at the
65 nm node.
Views from the Top: Lloyd J. LaComb Jr., Ph.D. Future Fab Intl. Volume 16, February 03, 2004
Dr. LaComb joined Veeco in July 1997, originally as director of operations in Tucson. Prior to joining Veeco, he was director of advanced development, as well as director of thin film engineering, for Tencor Instruments in Santa Clara, California. Most recently, he served as director of research and development for ALARA in Sunnyvale, California. Dr. LaComb holds a Ph.D. in applied physics from Stanford University.
Llyod J. LaComb, Jr. Ph.D., Veeco
A New CrossBeam Inspection Tool Combining an Ultrahigh Resolution Field Emission SEM and a High Resolution Future Fab Intl. Volume 15, July 11, 2003
Through the combination of the well known Gemini ultrahigh resolution field emission SEM column and the well known Canion31+ high performance FIB column a wide field of applications can now be accessed.
Peter Gnauck, Carl Zeiss SMT-Nano Technology, Peter Hoffrogge, LEO Electron Microscopy Group, Jens Greiser, LEO Electron Microscopy Group
Non-Destructive Detection of Voids in Metal Interconnect Structures Future Fab Intl. Volume 15, July 11, 2003
As device geometries shrink and metal
interconnects become narrower, the
increasing aspect ratio leads to difficulty filling the damascene structures without voids. This in turn is leading to new developments in metal deposition techniques and to new metrology strategies. In this work, void fraction was measured in tungsten vias and copper trenches using a newly developed application of non-contact SurfaceWave™ metrology. Correlation of void fraction with feature geometry and changes in the deposition process can be clearly seen showing the relevance of the measurement to on-line detection of process induced
voids.
Joshua Tower, Advanced Metrology Systems, Michael Gostein, Advanced Metrology Systems, Kolchl Otsubo, Advanced Metrology Systems, Atsushi Kawasaki, NEC Hiroshima
SECTION 7 INTRODUCTION, VOL 15: Metrology / Failure Analysis Future Fab Intl. Volume 15, July 11, 2003
The pervasive nature of nanotechnology and funding for nanotechnology make it a fertile ground for the search for new metrology including materials characterization. Since the previous editorial focused on potential developments in the area of metrology, this editorial will focus on materials characterization.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany, Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden, Prof. Dr. Christian Boit, Infineon Technologies AG
Barrier/seed Step Coverage Analysis in Via Structures for In-laid Copper Process Control Future Fab Intl. Volume 14, February 11, 2003
TEM-based techniques for barrier/seed step coverage analysis in via structures are reviewed. This challenging analytical task requires a dedicated sample preparation. The FIB technique makes it possible to prepare via cross-sections with high accuracy in a reasonable timeframe. The potential and the limits of brightfield and Z contrast imaging as well as of analytical TEM are discussed. The three-dimensional reconstruction of the object using electron tomography and the HAADF imaging of “inner surfaces” are new approaches to characterize the thickness and the uniformity of the barrier and sometimes of the seed layer at the most critical structures, the sidewalls of the vias.
Ehrenfried Zschech, Fraunhofer Institute for Nondestructive Testing; Dresden, Hans-Jürgen Engelmann, AMD, Heiko Stegmann, AMD, Holger Saage, AMD, Quentin de Robillard, AMD
Characterization of Gate Dielectrics Using Transmission Electron Microscopy Future Fab Intl. Volume 14, February 11, 2003
Transmission electron microscopy (TEM) and scanning-transmission electron microscopy (STEM) have become essential metrology tools in the semiconductor industry, and, in this paper, we show several examples of applications to gate dielectrics. TEM/STEM, in addition to providing a direct measure of layer thickness (in a gate stack, for example), is capable of yielding other information of interest including crystallinity, elemental composition, and chemical bonding/electronic structure data. Moreover, these data can be collected with a spatial resolution on the order of 1 nm.
J. Kulik, Motorola
Resistive Interconnection Localization Future Fab Intl. Volume 14, February 11, 2003
Resistive Interconnection Localization (RIL) is a new scanning laser microscope analysis technique that directly and rapidly localizes defective IC vias, contacts, and conductors from the front side and backside. RIL uses a scanned laser to produce localized thermal gradients in IC interconnections during functional testing. A change in the pass/fail state with localized heating of the IC identifies the failing site. The technique reduces the time to locate a resistive via from months to minutes. The sources of defective vias, the physics of RIL signal generation, and examples of RIL analysis are presented.
Edward I. Cole Jr., University of New Mexico, Paiboon Tangyunyong, University of New Mexico, Charles F. Hawkins, University of New Mexico, Michael R. Bruce, AMD, Victoria J. Bruce, AMD, Wan-Loong Chong, AMD, Rosalinda M. Ring, AMD
Advanced Deconstruction Methodology for Copper Wafers Future Fab Intl. Volume 13, July 08, 2002
A key method for yield learning is physical
failure analysis. Defects being analyzed by
PFA are often hidden beneath a multiple
level metalization stack and can be hardly
visualized from a bird’s eye view. In that
situation deconstruction processes come
into play enabling a controlled layer by
layer removal. Copper metalization
production processes, when introduced,
brought new challenges to the PFAcommunity,
which needed to be solved.
Christian Hobert, AMD
Overlay Metrology Development at International SEMATECH Future Fab Intl. Volume 13, July 08, 2002
International SeMaTech (ISMT) is a research
and development consortium established for
the purpose of developing leading edge
semiconductor processes and equipment. To
this end, the Overlay Metrology Advisory
Group (OMAG) was formed and has
collaborated to create a unified specification
for overlay measurement tools[1], overlay
standards, and materials support for further
development.
Michael Bishop, International SEMATECH, Beth Russo, Motorola
Smart Testing Interface: Innovative Low-Cost Tool for Defect Localization in ICs Future Fab Intl. Volume 13, July 08, 2002
 To respond to the needs of failure analysis
laboratories, we have developed a modular
smart test system. This Smart Testing
Interface can maintain a device in the proper
electrical state for defect localization and can
be easily adapted to a wide range of electrical
testers. It offers a unique combination of a
slave and a stand-alone mode.
In slave mode, a non-disruptive interface
exists between the tester and the
component. In stand-alone mode, an
electrical stimuli generator keeps the device
under test in the correct internal electrical
state during IC defect localization.
P Perdu, CNES - French Space Agency, R Desplats, CNES - French Space Agency
Failure Analysis From the Back Side of a Die Future Fab Intl. Volume 12, February 02, 2002
The photoemission microscope (PEM) is a tool for localization of defect sites within integrated circuits. The PEM analysis is based on the detection of weak electroluminescent radiation that is emitted from defects in integrated circuits as visible and infrared (IR) light. Most defect types emit wavelengths between 500 and 1300nm. Because of the transparency of silicon in the near IR it is possible to detect failures from the back side of the device.
Silke Liebert, Advanced Metrology Systems
Future Concerns In 300mm Metrology Future Fab Intl. Volume 12, February 02, 2002
Ultimately, the quality of a semiconductor manufacturing process is reflected in the number of fully functioning die produced. Metrology operations are therefore required to provide the in-line checks to ensure engineering that the devices being built are meeting the required specifications, which leads to a functional device at the end of the manufacturing process. Without these intermediate checks only the end product testing would determine proper unit construction.
Michael G McIntyre, AMD
Inline Failure Analysis on Productive Wafers with Dual Beam SEM/FIB Systems Future Fab Intl. Volume 11, June 29, 2001
Thomas E West, Thomas West , R Weiland, Infineon Technologies AG, Prof. Dr. Christian Boit, Infineon Technologies AG, Bernd Ebersberger, Infineon Technologies AG, S Geyer, Infineon Technologies AG, A Hirsch, Infineon Technologies AG, P Meis, Infineon Technologies AG, M Kamolz, Infineon Technologies AG, H Rettenmaier, Infineon Technologies AG, W Tittes, Infineon Technologies AG, R Treichler, Siemens IBC , H Zimmermann, Silicon Valley Group
Overlay Metrology: Recent Advances and Future Solutions Future Fab Intl. Volume 11, June 29, 2001
Richard M. Silver, National Institute of Standards and Technology, J Jun, National Institute of Standards and Technology, S Fox, National Institute of Standards and Technology, E Kornegay, National Institute of Standards and Technology
Scanning Probe Microscopy in Semiconductor Failure Analysis Future Fab Intl. Volume 11, June 29, 2001
Bernd Ebersberger, Infineon Technologies AG, A Olbrich, Infineon Technologies AG, Prof. Dr. Christian Boit, Infineon Technologies AG
Integrated Yield Management Tools for Rapid Yield Learning Future Fab Intl. Volume 10, July 01, 2001
Fred Lakhani, International SEMATECH
Non-destructive, High-resolution Metrology of Fine Metal Arrays Future Fab Intl. Volume 10, July 01, 2001
Peter Borden, Boxer Cross
X-ray Reflectometry Characterization of Ultrathin High-k Gate Oxide Materials Future Fab Intl. Volume 10, July 01, 2001
Prasa Alluri, Motorola , Joseph Formica, Jordan Valley Semiconductors, Inc.
Absolute Contaminant and Haze Standards for Wafer Surface Inspection System Calibration Future Fab Intl. Volume 9, January 07, 2000
James Sun, MSP Corporation
Non-Destructove Characterization of Activated Ultra-Shallow Junctions Future Fab Intl. Volume 9, January 07, 2000
Peter Borden, Boxer Cross, Laurie Bechtler, Boxer Cross, Lawrence Larson, Texas State University at San Marcos, TX
The Future of the SEM for Image and Metrology Future Fab Intl. Volume 9, January 07, 2000
David Joy, EM Facility University of Tennessee & Oak Ridge National Laboratory
Time-of-Flight Secondary Ion Mass Spectrometry: Semiconductor Surface Analysis for a New Millennium Future Fab Intl. Volume 9, January 07, 2000
Steven Hues, Motorola , Scott Bryan, Physical Electronics
Contact Angle Mapping Tool Future Fab Intl. Volume 8, July 01, 2000
KRÜSS,
Implementation of an Improved Equipment Defectivity Monitoring Scheme in a Deep Sub-micron Fab Future Fab Intl. Volume 8, July 01, 2000
Benoit Hinschberger, STMicroelectronics , Christine Gombar, STMicroelectronics
Moving to post-180 Nanometre Process Technology Future Fab Intl. Volume 8, July 01, 2000
Alec Reader, Philips Analytical, Laurens Kwakman, STMicroelectronics
Reference™ Spectroscopic Ellipsometer for On-Line Characterisation Future Fab Intl. Volume 8, July 01, 2000
J-L Stehle, SOPRA, L. Tantart, SOPRA, C. Defranoux, SOPRA, T. Emeraud, SOPRA, J. Trihle, STMicroelectronics
Spectroscopic Ellipsometry in the Vacuum Ultraviolet: 157 nm and Below Future Fab Intl. Volume 8, July 01, 2000
James Hilfiker, J.A. Woollam Co., Inc.
The Industrial Use of Synchrotron Radiation Future Fab Intl. Volume 8, July 01, 2000
Fabio Comin, ESRF
Thin Film XRF Metrology Tool for IC Fabs Future Fab Intl. Volume 8, July 01, 2000
Rien Stoop, Philips Analytical Almelo
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