Section 8 Introduction: Final Manufacturing Future Fab Intl. Volume 23, July 09, 2007
As volume electronic manufacturing in the U.S. continues to decline, the need to find new and innovative products, technologies and solutions grows increasingly more important to sustaining the industry in the U.S.
Steve Greathouse, Plexus Corporation

 Manufacturing and Application of ‘Interconnect Via-Based 3D’ Future Fab Intl. Volume 23, July 09, 2007
Recently various kinds of new materials for forming active devices can be stacked on the CMOS interconnect layers, and they are connected to other active devices through interconnect via. This technology realizes “interconnect viabased 3D.”
Shinobu Fujita, Toshiba Corporation

 Testing 3D Stacked Devices Future Fab Intl. Volume 23, July 09, 2007
Stacking die can no longer be treated like chips on a board. The new bonding techniques and new DFM and yield issues with bare die have brought into question the concept of known good die (KGD).
Al Crouch, ASSET InterTech, Inc.

 Through Silicon Vias: Building a Bridge Between Fab and Packaging, and Paving the Road(map) Future Fab Intl. Volume 23, July 09, 2007
3D integration is a fast-growing field that can encompass many different types of processes. In this paper, the term refers to any process flow that contains more than one device layer. For example, a second layer of devices can be formed on a wafer by adding a layer of polysilicon or amorphous silicon, which subsequently is processed to form load transistors.
Susan Vitkavage, SEMATECH

 Managing Post-Production Test Data Future Fab Intl. Volume 22, January 09, 2007
Data collection during production test and data post-processing is getting the growing attention of the semiconductor industry. Several recent international technical forums hosted panel sessions and presentations on the data collection issue, and tester vendors are receiving multiple requests for expanded data collection capabilities. Two main trends can be held responsible for this. The first trend is to analyze the production test data off-line by statistical methods, e.g., to identify reliability risks and to reduce or replace burn-in. The second trend is to generate data for yield learning purposes.
Mr. Paul Roddy, Advantest , Andreas Leininger, Infineon Technologies AG

 A Model for Determining ATE Cost of Ownership Future Fab Intl. Volume 22, January 09, 2007
In the competitive arena that defines semiconductor automatic test equipment (ATE) decision making and selection, once equipment is proven to be technically capable of providing the necessary test coverage for a customer’s device, the critical deciding factor becomes the equipment’s cost of ownership (CoO). Since there may be more than one technically viable solution, equipment selection is most often determined by CoO. Technical differentiation does, of course, exist. However, now more than ever, technical differentiators are revealed in the form of cost advantages, rather than a simple ability vs. inability to test the part.
Doug Lefever, Advantest

 Modeling of Chip Package Interaction in Cu/Low-k Flip Chip Packages Future Fab Intl. Volume 22, January 09, 2007
Chip-Package-Interaction (CPI)-induced BEOL (Back end of line) delamination has emerged as a major reliability concern with the adoption of Cu/low-k as the mainstream BEOL technology. To study the dependence of Cu/low-k delamination on package underfill material properties and BEOL stackup configuration, a multilevel finite element analysis modeling technique was developed to perform fracture mechanics analysis for a high performance organic flip chip package with Cu/low-k back-end technology. The analysis demonstrated that the reduced elastic modulus of the inter-layer dielectric led to greater probability of CPIrelated delamination for both failure modes. Replacing oxide with low-k dielectric resulted in a 3x increase of energy release rate. Hybrid BEOL stackup can effectively reduce the energy release rate by approximately 40 percent versus all low-k BEOL stackup. The modeling also indicated that die size is not the limiting factor for CPI reliability.
Charlie Zhai, Advanced Micro Devices, Raj N. Master, Advanced Micro Devices, Michael Z. Su, Advanced Micro Devices

 Making the Business Case for 3D Future Fab Intl. Volume 22, January 09, 2007
A red brick wall is looming in the Interconnect chapter of the International Technology Roadmap for Semiconductors (ITRS), a barrier caused by the difficulty integrating porous low-k dielectrics, combined with the rising resistivity of the copper interconnect system. As consumers demand more functionality in smaller spaces, the industry is considering interconnect as a possible solution to the copper-low-k conundrum. Just as spacechallenged architects sparked the skyscraper boom in the early 1900s, chip designers may look to the third dimension now that chip real estate is at a premium. But will a 3D architecture be costeffective? What must we do to understand the potential benefits and pitfalls? When the analysis is complete, will Interconnect be the next great thing – just a niche technology? This article addresses these and other questions about one of our industry’s hottest emerging technologies.
Susan Vitkavage, SEMATECH

 Importance and Benefits of the OPENSTAR® Ecosystem: How Industrywide Open Test Architecture Is Critical to the Ongoing Vitality of the Semiconductor Business Future Fab Intl. Volume 21, July 01, 2006
In 2002, emerging from the worst downturn the semiconductor industry had ever experienced and propelled by consumer mass-market IC demand, a group of pioneering semiconductor, equipment and instrumentation companies founded the Semiconductor Test Consortium (STC) to develop an industrywide open test architecture. Now with over 80 international members and growing monthly, in three short years the nonprofit STC has established a number of ongoing technical working groups in areas as diverse as hardware, software, probe cards and STIL, the IEEE’s Standard Test Interface Language standard; developed and published Open Semiconductor Test Architecture (OPENSTAR®) hardware and software specifications; and held its first global conference to advance development of the OPENSTAR Ecosystem.
Sergio Perez, Advantest , Keith Imai, Advantest

 INTRODUCTION SECTION 9 - FINAL MANUFACTURING Future Fab Intl. Volume 21, July 01, 2006
The big day is here: The European ROHS directive to eliminate six different materials, including lead, in new products has had an impact on every electronics manufacturer worldwide. The cost and effort to implement this change has been overwhelming. This was probably the biggest conversion of materials and systems ever encountered in the electronics industry. This has impacted everything from die and package assembly materials, their related processes, handling, shipping and storage methods, as well as bare boards (now with immersion silver finish), the hundreds of components from an unending list of suppliers, the individual component reliability qualifications and certifications, the Supplier Documents of Conformance (SDOCs) that have to be generated and kept on file by every final system manufacturer, and even impacts the part numbers and the ordering systems that the customers access. We are not through yet. Now the work of eliminating Halogen materials is our challenge.
Steve Greathouse, Plexus Corporation

 Wafer Level Packaging: More Than IC Packaging Future Fab Intl. Volume 21, July 01, 2006
In recent years, four different CSP categories were defined to distinguish the commercializable approaches for this upcoming packaging approach: rigid and flex interposer as miniaturized BGA, lead -frame-based and wafer level. Economic considerations have been driving packaging technologies toward the concept of wafer level packaging (WLP) to finalize and test the package for each die before singulation. The transition to 300 mm wafer size pushed the solution to finalize as much of the packaging sequences on wafer level as possible. WLP became an economic solution for low pin count passives, EEPROM, flash, DRAM, ASICs and microprocessors. Area array for the interconnect is further necessary to match the I/O pitch of the IC to the routing density of the printed circuit board (PCB) which is necessary to combine the different components or modules for microelectronic systems. Redistribution technology established 10 years ago is therefore an essential process step for WLP.
Michael Topper, TU Berlin Microperipherics Center

 Wafer Level Packaging: Yesterday, Today and Tomorrow Future Fab Intl. Volume 21, July 01, 2006
As the world’s demand for portable electronics has accelerated, the need to make semiconductors smaller, faster, lighter and cheaper has never been greater. No longer are traditional semiconductor packaging technologies sufficient to meet the needs of the mobile electronic device manufacturers. As witnessed by the dramatic evolution of cellular phones, product differentiation today is driven by ever-expanding functionality, feature sets and faster communications. At the same time, consumers have made clear their desires for feature-rich products in compact form factors to enable maximum portability. Wafer level packaging is successfully enabling leading semiconductor manufacturers to provide the smallest possible, highest-performing semiconductors.
Ravi Chilukuri, Amkor Technology Inc., David Hays, Amkor Technology Inc.

 Application-Specific Reliability in New Product Applications Future Fab Intl. Volume 20, January 07, 2006
Whenever new products are introduced into the marketplace, there are always questions about how to ensure that the product functions and performs as expected in the customer’s application for the length of time that is expected. With this objective in mind, what is the amount and type of testing that needs to be done to establish the expected reliability of the product in its final field application? How is this test criteria established?
Steve Greathouse, Plexus Corporation

 Laser-Microjet Ready for Dicing of GaAs Wafers Future Fab Intl. Volume 20, January 07, 2006
After successful integration of the Laser-Microjet in machining of thin silicon wafers (dicing and edge grinding), the technology has now entered the field of compound semiconductors with a laser dicing system for GaAs wafers. Following several months of test runs, the laser dicer is now ready for production. RF Micro Devices adopted the Laser-Microjet system because of its speed, cleanliness, absence of chipping or cracking, small kerfs and minimization of environmental issues.
Delphine Perrottet, Synova SA, Roy Housh, Synova SA, Dr. Bernold Richerzhagen, Synova SA

 Redefining the Test Equipment Supply Chain: The Open Architecture Revolution Future Fab Intl. Volume 20, January 07, 2006
As the automated test industry begins embracing the open architecture environment, equipment suppliers and their customers will need to evolve equipment development methodologies to fully benefit from the emerging business model.
Jason Katz, Intel Corporation, Don Edenfeld, Intel Corporation

 SECTION 9 – INTRODUCTION: FINAL MANUFACTURING Future Fab Intl. Volume 20, January 07, 2006
The state of the economy for the electronics industry is in good shape, but as always, very cost-competitive. In the semiconductor electronics industry, new and existing products that are facing heavy pressure for cost reduction are always faced with the same question about how to build the best functional and cost-effective product in a package. Should they use a combination of die inside a plastic package (a “system in a package,” or SIP) or should they try to design one die in the package that does it all (often called a “system on a chip” or SOC)? There really isn’t an answer that is the same for every case.
Steve Greathouse, Plexus Corporation

 Cost of Test: The Big Driver in ATE Future Fab Intl. Volume 19, June 28, 2005
ATE suppliers have been confronted by cost-of-test issues for as long as this industry has been in existence. Some of VLSI Research’s earliest projects involved cost of test in the late ’70s, and we have been asked to cover the topic from time to time by ATE suppliers as well as ATE users. Each time the cost-of-test issue has emerged as a major discussion point in ATE, the industry has made significant changes on how testers are architected or how test strategies are developed. Examples include the emergence of tester-per-pin architecture, parallel testing, functional- at-speed testing, iddq, DFT and single-platform tester architecture.
Risto Puhakka, VLSI Research Inc.

 Development and Industrialization of Matte Tin Coating on Copper for Lead-Free Semiconductors (E4 Initiative) Future Fab Intl. Volume 19, June 28, 2005
Conversion of electronic components to lead-free technology is taking place and for several companies will be completed in the next few quarters. This is the case for semiconductor manufacturers of the E4 Initiative: Freescale, Infineon, Philips and ST.
Carlo Cognetti, STMicroelectronics , Sheila Chopin, Freescale Semiconductor, Peng Su, Freescale Semiconductor, Jan van de Water, Philips Semiconductors, Pascal Oberndorff, Philips Semiconductors, Juergen Winterer, Philips Semiconductors, Marc Dittes, Infineon Technologies AG

 Introduction: Final Manufacturing Future Fab Intl. Volume 19, June 28, 2005
The full implementation date for new products to meet the Pb-Free ROHS requirements is only a year away. Most electronic industry manufacturers are now heavily involved in the details of certifying or qualifying their products with their chosen lead replacement material. In most cases, this is a tin/silver or tin/silver/copper compound being used in solder paste or a wave solder configuration. The questions that most companies are trying to answer can be summarized as, are the new replacement materials as reliable as the old lead containing solders in my application? How do I test my product to see if it is reliable? What stresses do I perform? How do I make sure I don’t overstress the parts and create false failures? What will my customer expect of my product in his application?
Steve Greathouse, Plexus Corporation

 Long-Term Consequences of ‘Green’ Electronics Not to Be Forgotten Future Fab Intl. Volume 19, June 28, 2005
The deadline for the European legislation on the restriction of hazardous substances (RoHS) looms at the horizon. Everybody involved knows by now, or is at least supposed to know, that from July 2006 on, almost all electronics put on the market should be RoHS compliant. In the electronic soldering and assembly business, this roughly equals saying that everything should be lead-free. More and more, alternatives for the tin-lead (SnPb) era appear in literature and even on the market. Consumer electronics in Japan are fully converted to “green,” and sales figures indicate that people are more than eager in their choice for “environmentally aware” products. But in the race to be the first on the market, commercial companies may have the tendency to focus on short-term issues and pay less attention to the possible long-term effects of the adaptations made in their technology. But then again, it’s not the industry that should be blamed, as it merely operates toward consumer and legislative demands.
Petar Ratchev, imec, Koen Snoeckx, imec, Bart Vandevelde, imec

 Open-Architecture ATE vs. Traditional ATE Future Fab Intl. Volume 19, June 28, 2005
Today, the automated test equipment (ATE) industry is facing a technological revolution in which emerging open-architecture test is competing with traditional ATE. It's conceivable that, in the near future, open-architecture ATE systems will eventually replace the traditional ATE systems that currently dominate the test landscape. Open-architecture ATE can offer practical solutions to the challenge of cost-effectively testing systems-onchip, systems-in-package and other complex semiconductor devices. At the same time, it delivers such benefits as reconfigurability, flexibility, scalability and expandability, while accommodating accelerating test requirements, lowering cost of ownership and lengthening testsystem life cycles.
Yuhai Ma, Advantest

 Thin Wafer Dicing Issues and New Technology Cost of Ownership Future Fab Intl. Volume 19, June 28, 2005
According to market experts, the thin wafer market will grow 3 to 30 percent by 2007. This growth is fueled in large part by the ability of thin wafer technology to allow staked packaging for the IT industry and significantly improved power dissipation for power devices – a critical requirement for reducing die size. Thin wafer technology increases the function density of IC packaging to enable the development of more portable electronics. To ensure rapid growth of the thin wafer market, the semiconductor industry requires a new method for highquality, low-cost wafer dicing. Synova SA has developed a water-jet-guided laser wafer dicing system to meet this need.
Dr. Weimin Liang, International Rectifier

 Benefits Of A True ‘Open Architecture Tester’ Model Future Fab Intl. Volume 18, January 12, 2005
Semiconductor manufacturers are driving a new paradigm shift in semiconductor testing! Fed up with trying to efficiently manage test floors filled with a variety of tester models from multiple vendors, semiconductor manufacturers have started an initiative to drive development of an "open architecture tester" model. Although somewhat reluctant, the tester equipment vendors are responding to this user effort.
Paul Roddy, Freescale Semiconductor

 Lead-Free Second Level Interconnect On Flip-Chip Packages Future Fab Intl. Volume 18, January 12, 2005
In a flip-chip package, lead is used in passive component termination finish (SnPb plating), SnPb solder paste for connecting die/land-side capacitors to the board, ball grid array (BGA) solder balls and a high lead-bearing solder bump on silicon that is connected to substrate using eutectic SnPb solder (first level interconnect or FLI). The scope of this paper does not include the FLI silicon chip attach. Figure 1 summarizes the changes made in the flip-chip BGA package to meet the RoHS requirement.
Vivek Gupta, Intel Corporation, YT Chin, Intel Corporation

 Low-Cost Wafer Bumping Using C4NP Future Fab Intl. Volume 18, January 12, 2005
As flip chip interconnects continue to gain on wire bond, several wafer bumping processes have been developed to produce the small solder features required for this technology. These processes vary significantly in complexities and commensurate costs. Whereas most low-cost methods have limitations regarding extendibility to larger wafers and smaller bump sizes and pitches, they do provide process simplicity and alloy flexibility that is attractive for current Pbfree efforts. Recently, a new bumping process developed at IBM Research called C4NP, also known as injection molded solder (IMS), has shown the capability to combine low-cost attributes with highend capabilities, a potentially very powerful combination.
Barry Hochlowski, IBM Microelectronics Division, Dave Naugle, IBM, Peter Gruber, IBM

 Open Architecture Testers – Year One: Does Reality Match The Vision? Future Fab Intl. Volume 18, January 12, 2005
Intel’s test equipment roadmap is complex and very difficult to manage. We have over 1,000 high-end automatic test equipment (ATE) testers running more than 1,000 products across a worldwide factory and engineering site network. The costs associated with purchasing, support, training, etc., run into multi-billion dollars and represent a significant portion of product test costs. In addition, most of these platforms are five to 10 years old, making the fleet increasingly costly to maintain.
John Johnson, Intel Corporation, Don Edenfeld, Intel Corporation, Jim Neeb, Intel Corporation

 SECTION 9: INTRODUCTION Future Fab Intl. Volume 18, January 12, 2005
It is the innate nature of humans to be reluctant to change. Once a method, theory, or practice has been learned, people feel comfortable and don’t want to spend the effort (or in many cases, the money) to make the change. Even if the new method is vastly superior, they are very reluctant to accept anything new.
Steve Greathouse, Plexus Corporation

 SECTION 9: INTRODUCTION Future Fab Intl. Volume 18, January 12, 2005
Evolution of silicon technology to finer lithography rules and the ability to include increased functionality and complexity on silicon have profound impacts on back-end manufacturing and technology. Gone are the days when back-end manufacturing was taken for granted. Technology, reliability, cost and environmental regulations require that leadingedge solutions be developed. The key to developing solutions requires that equipment, materials and process solutions be developed jointly between suppliers and users. This section addresses three distinctly separate elements of such solutions.
Raj N. Master, Advanced Micro Devices

 Water-Jet-Guided Laser Achieves Highest Die Fracture Strength Future Fab Intl. Volume 18, January 12, 2005
While less than 5 percent of today’s semiconductor wafers are thin (<150 µm), in the next two years that percentage could increase to 20 or 30 percent. In addition to offering thinner packages, thin wafers also provide improved heat evacuation and a certain degree of flexibility. However, the flexibility achieved for dies based on these wafers depends significantly on die fracture strength. This is the result of two factors: surface fracture strength and edge fracture strength. After applying precise stress release methods like chemical mechanical polishing, spin etching and dry polishing, which remove damage on the backside of the wafer after grinding, die fracture strength is currently determined primarily by edge fracture strength. The next step toward increased die strength is, thus, to improve dicing.
Delphine Perrottet, Synova SA, Jean-Marie Buchilly, Synova SA, Dr. Bernold Richerzhagen, Synova SA, Werner Kröninger, Infineon Technologies AG

 Challenges in Flip Chip Packaging of Low-k Die Future Fab Intl. Volume 17, June 21, 2004
Microprocessor designs are getting complex and challenging as we move from one generation to the next. This is due to the need to get higher clock speeds and to have more functionality built into the chip. The number of transistors per unit area keeps increasing while the chip size is shrinking. Continuous improvements in manufacturing design rules and new process technologies is required to deliver a cost-effective and high-performance product in the marketplace.
Raj N. Master, Advanced Micro Devices, Srinivasan Parthasarathy, Advanced Micro Devices

 Characterization of an Ultra-Thick Positive Photoresist for Electroplating Applications Future Fab Intl. Volume 17, June 21, 2004
The performance requirements for ultra-thick photoresists have increased rapidly with the dramatic growth in new lithographic applications that require electroplating processes. Two of the main applications for ultra-thick photoresists are nanotechnology (MEMS) and advanced packaging. Flipchip packaging has become widely adopted to address electrical device performance and chip form factor considerations. The growth in the nanotechnology market is driven by a wide range of products, which include accelerometers, ink jet print heads, biomedical sensors and optical switches.
Warren W. Flack, Ultratech, Ha-Ai Nguyen, Ultratech, Elliott Capsuto, Shin-Etsu MicroSi, Inc.

 Contrast Enhancement Materials for Thick Photoresist Applications Future Fab Intl. Volume 17, June 21, 2004
The performance requirements for ultra-thick photoresists are rapidly increasing due to the dramatic growth of applications such as nanotechnology (MEMS) and advanced packaging. Commercial products such as accelerometers, ink jet print heads, biomedical sensors and optical switches are driving growth in the nanotechnology market. Advanced packaging techniques such as flip chip in package, flip chip in board and wafer level chip scale packaging have become widely adopted to address electrical device performance and chip form factor considerations.
Warren W. Flack, Ultratech, Ha-Ai Nguyen, Ultratech, Jim Buchanan, Ultratech

 Damage-Free Dicing of Low-k Wafers Future Fab Intl. Volume 17, June 21, 2004
A few years ago, the constant need of better die performance, has led researchers in the semiconductor field, to turn toward new materials with a low dielectric constant (k<3.0). Use of materials with a k value lower than SiO2 has reduced the capacitance of the interconnect structure. In tandem with the replacement of aluminum, interconnects with copper (Cu) reducing structural resistance, paving the way for this major improvement by permitting a marketrelevant reduction of the interconnect delay.
Julien Vittu, STMicroelectronics , Delphine Perrottet, Synova SA, Jean-Marie Buchilly, Synova SA, Dr. Bernold Richerzhagen, Synova SA

 Dual Side Wafer Metrology for Micromachining Applications Future Fab Intl. Volume 17, June 21, 2004
Advances in micromachining (MEMS) applications such as optical components, inertial and pressure sensors, fluidic pumps and radio frequency (RF) devices are driving lithographic requirements for tighter registration, improved pattern resolution and improved process control on both sides of the substrate. Consequently, there is a similar increase in demand for advanced metrology tools capable of measuring the Dual Side Alignment (DSA) performance of the lithography systems.
Daniel Schurz, Ultratech, Warren W. Flack, Ultratech, Doug Anberg, Ultratech

 Reliability of Electroplated Lead-Free SnAg Bumps for Flip Chip Applications Future Fab Intl. Volume 17, June 21, 2004
Electroplated lead-free tin-silver (SnAg) solder bumps are shown to be a suitable solution for environmentally friendly (“green”) flip chip packages. Extensive investigations have been carried out to ensure the reliability of this new solder material in challenging flip chip applications. All degradation mechanisms are taken into account by appropriate tests. Main contributors to degradation of solder bumps are temperature and current stress, while mechanical and thermo-mechanical stress must be absorbed by the flip chip package in which the bumps are embedded.
Bernd Ebersberger, Infineon Technologies AG, Robert Bauer, Infineon Technologies AG, Lars Alexa, Infineon Technologies AG

 Section 9 Introduction, Vol. 17: Final Manufacturing Future Fab Intl. Volume 17, June 21, 2004
Two of the many challenges facing the semiconductor assembly and packaging industry today are: assembling low-k dielectric products and the conversion to lead-free solders for packageinterconnect. Much is already known about these two areas, but as these processes get into production, many problems will crawl out of the woodwork that have not been addressed before.
Steve Greathouse, Plexus Corporation

 Ultra-Low-k Challenges in the Wire Bond Process Flow Future Fab Intl. Volume 17, June 21, 2004
The packaging of ultra-low-k devices provides significant challenges due to not only the ultra-low-k materials but also due to the continued pressure to shrink the die sizes and therefore reduce cost. Significant process and materials changes will have to occur to address the stress reduction and performance issues in the ultra-low-k materials.
Richard Groover, Amkor Technology Inc.

 Emerging Materials Challenges in RF Electronic Packaging Future Fab Intl. Volume 16, February 03, 2004
The trend for microelectronic devices historically has been, and will continue to be, toward smaller feature size, faster speeds, more complexity, higher power, and lower cost. The motivating force behind these advances traditionally has been microprocessors. With the tremendous growth of wireless telecommunication, RF applications are beginning to drive many areas of microelectronics traditionally led by the development of the microprocessor. An increasingly dominant factor in RF microelectronics is electronic packaging and the materials needed to create the package, because the package materials strongly affect the performance of the RF electronics. Highlights of the key issues facing electronic packaging of RF packages are discussed in this paper.
D.R. Frear, Motorola

 Laser-Edge Grinding of Thin Wafers with the Water-Jet-Guided Laser Future Fab Intl. Volume 16, February 03, 2004
During the past 10 years, the Laser Microjet® (water-jet-guided laser) has been continuously optimized, responding to specific market demands, which are increasingly more diversified and ever more demanding. Due to chip volume optimization and technical requirements, the semiconductor industry is obliged to reduce the wafer thickness. Wafer handling is extremely critical for silicon wafers with thicknesses less than 100 microns, due to the brittleness of the wafer edge. The fragility of the wafers is due to micro-cracks omnipresent along the edge, tending to propagate when subjected to the slightest mechanical solicitation.
Ochelio Sibailly, Synova SA, Dr. Frank Wagner, Synova SA, Dr. Bernold Richerzhagen, Synova SA

 SECTION 8 INTRODUCTION, VOL 16: Final Manufacturing Future Fab Intl. Volume 16, February 03, 2004
There is an old saying that states that the only thing you can always count on is change. Mostly, change is good. There are times, however, when a radical change completely removes the old and takes over. A good example of this is the ice industry of the 1800s and early-1900s in the United States and Europe. Many of our great-grandmothers would talk about the icebox that everyone had in their kitchen and how they would wait for the iceman to come with his horse-drawn wagon, selling the ice for 10 cents for a medium-sized chunk. He would bring the chunk of ice into the house holding it with large ice tongs that pierced the ice so it wouldn't drop. Huge storage buildings had been built to store the ice that had been laboriously cut from the winter lakes. These buildings were insulated with heavy layers of sawdust and, in most cases, were recessed into the ground to keep the warmer summer air from melting the ice. Many full-size cargo ships were built to transport huge shipments of ice from the frozen freshwater lakes in northern Canada to the railcars at U.S. harbors for distribution to cities and homes around the country. This was a vast industry with hundreds of thousands of workers involved in the business.
Steve Greathouse, Plexus Corporation

 Advances in 1x Full Field Lithography Systems for Wafer Level Packaging Future Fab Intl. Volume 15, July 11, 2003
The inherent cost advantage, flexibility, and ease of use of production of 1X full field lithography systems make them extremely attractive solutions for a wide range of lithography processes. Most importantly, 1X full field lithography (1XFFL) has been proven especially well suited for production processes where either the resist thickness or wafer topography exceeds several microns and ranges up to several hundred microns. This capability is at the heart of enabling technology for wafer level packaging, MEMS and opto-electronics. These systems are extremely reliable and have the capability to deliver significant lithography performance at low CoO. But, just as with any other technology, the user needs to understand and optimize the entire lithography process to obtain the maximum benefit. Advances in photomask and pellicle technology resist technology, coat/bake/develop systems and the exposure systems themselves have further enhanced the overall capabilities of these systems and expanded their use to 300mm production. This work will examine the key advances in 1XFFL that have enabled its use in leading-edge wafer level bumping and redistribution applications.
James Hermanowski, Süss MicroTec AG

 Applications of Simulation Modeling at Texas Instruments DMOS5 Wafer Fab Future Fab Intl. Volume 15, July 11, 2003
TI launched a fabwide CT reduction initiative in 2001. As a result, all the modules in DMOS5 identified cycle time reduction projects in their respective modules that target cycle time reduction.
Amit Gupta, Texas Instruments Incorporated, Kishore Potti, Texas Instruments Incorporated

 Dicing of GaAs Wafers -Security and Yield Issues: What Dicing Technologies Have to Offer? Future Fab Intl. Volume 15, July 11, 2003
Today the Gallium Arsenide (GaAs) IC market has reached an important volume. But what are the dicing solutions offered to GaAs chip manufacturers? Are the standard dicing technologies adapted to this particular material? Three dicing methods will be reviewed and compared: the abrasive saw, scribing and breaking, and Laser-Microjet® (LMJ) dicing.
Laetitia Mayor, Synova SA

 Production Enhancement of Lithography Through APC Methods Future Fab Intl. Volume 15, July 11, 2003
Productivity improvement is an inherent part of our business. A major aspect thereof is the switch to the 300mm wafer size. This is a very cost intensive measure that is economically reasonable mainly for memory-IC production. In recent years the semiconductor industry has discovered advanced process control (APC) as an effective measure to enhance productivity. Lithography is one of the areas where APC can support both product and process engineers in manufacturing enhancement. This article describes how Infineon has used the APC approach in the lithography department.
Joern Maeritz, Infineon Technologies AG, Armin Schels, Infineon Technologies AG

 SECTION 8 INTRODUCTION, VOL 15: Final Manufacturing Future Fab Intl. Volume 15, July 11, 2003
As the electronics industry continues to move forward, in spite of still being in the worst downturn in the industry’s history, exciting new technologies and products are being exhibited with tantalizing displays of speed and convenience that amaze everyone. Read more.
Steve Greathouse, Plexus Corporation

 A Real world Application Used To Implement A True IDDQ Based Test Strategy Future Fab Intl. Volume 14, February 11, 2003
This paper discusses the results of introducing a true IDDQ based test strategy in a production test environment. The objectives of the project were to increase wafer sort test quality and product quality, increase overall test coverage without the need for expensive tests, reduce overall tests costs and pave the pathway for volume testing using a low-cost DFT tester platform. the experiments were carried out using a dedicated test chip and a commercial product as test vehicles on a HP83K machine. A commercially available loadboard IDDQ monitor was used to perform the IDDQ measurements. The project results show that a proper use of IDDQ testing not only serves to improve product quality but, in combination with proper measurement hardware, also serves to considerably reduce test time and costs.
Hans Manhaeve, Q-Star Test, Joseph S. Vaccaro, Motorola , Loren Benecke, Motorola , David Prystasz, Motorola

 Gentler and Faster: Infineon’s Subsidiary Eupec Uses the Laser Water-Jet (LaserMicrojet) for Separating Future Fab Intl. Volume 14, February 11, 2003
It is almost impossible to take a look at production plants in the semiconductor industry. This is an industry that doesn’t like to tip its hand, and that’s no different with high-performance semiconductors. One of the major reasons for its success on the market is its type of production. For instance, we know that lasers have occasionally been used in various places during the last 20 years to separate wafers, but nobody has ever seen these systems.
Franz J. Gruber , Eurolaser

 Packaging Automation: Opportunities at the “Back-end of the Back-end” Future Fab Intl. Volume 14, February 11, 2003
Over the past decade, the semiconductor industry has witnessed sweeping changes in nearly every arena throughout the postwafer fabrication “back-end” production and packaging segment. Successive waves of automation and innovation have completely transfigured the critical backend processes that turn un-singulated wafer-level die into the various finished component types needed for use in a wide range of final product assemblies. The increasing use of automation has boosted throughput both by speeding up individual operations and by enabling multiple operations to be conducted in parallel. In addition, the emergence of industrystandard transport methods, such as JEDECtrays, cassettes, magazines, etc., also have improved throughput by standardizing the inputs and outputs between automated processing cells. However, at the same time, the challenges of automating the back-end have been exponentially escalating along with the proliferation of new advanced packaging techniques and device types.
Remy Degen , Ismeca Europe Semiconductor S.A.

 Transforming the Final Test Floor Future Fab Intl. Volume 14, February 11, 2003
The reduction of cost-of-test has been a constant theme in the semiconductor industry. Besides having to cope with rising processing and equipment cost, semiconductor manufactures and the contract test and assembly providers are faced with constantly decreasing ASP (average selling price) for their products. In addition, packaging technologies are evolving very rapidly with new packages appearing in the market almost every other months or weeks. This is especially true with the use of chip scale packages (CSP) which is growing at a phenomenal rate. This has put a tremendous strain on the conventional test handling strategies, which are finding it difficult to cope with the varied geometry of these packages, as well as the demand for higher throughput. This paper discusses the emergence of new generation test handling equipment that has surfaced in the market, which holds great promise for solving the cost-of-test equation. The equipment promotes high parallelism testing by either adopting a strip-based or matrix-based handling approach. This, together with automation solutions currently available will go a long way in helping the test floor managers realize their cost reduction goals.
Kenneth Tay , ASM

 300mm Wafer Bumping Future Fab Intl. Volume 13, July 08, 2002
As the semiconductor wafer fabrication industry scales up to 300mm (12-inch) wafers, backend services and processes must adapt and accommodate the larger size. One such service for flip chip package assembly is wafer bumping, a necessary step for creating interconnects between chip and substrate. Though often the equipment and processes to handle these wafers can simply be scaled up from 200mm (8-inch) processing, some steps are not so direct. In the case of wafer bumping, preserving UBM/bump composition consistency and height uniformity across the whole wafer is a major concern.
Feng-Lung Chien, Siliconware Precision Industries Co. Ltd, Eric Ko, Siliconware Precision Industries Co. Ltd, Kevin Chen, Siliconware Precision Industries Co. Ltd, Andrea Chen, Siliconware Precision Industries Co. Ltd

 Effective Automation In Assembly and Test Future Fab Intl. Volume 13, July 08, 2002
The implementation of manufacturing cells and process integration has been going on in the wafer fabrication areas for many years. The results, improved quality and process control, speak for themselves when one examines the complexity and cost of today’s IC devices. The same factors that drove wafer fabrication are now driving assembly. This paper addresses the trend toward increased assembly integration by connecting manufacturing equipment to form in-line-manufacturing cells or flow lines.
Charles J Vath, III, IMAPS

 Equipment Automation and Controls for the Future Future Fab Intl. Volume 13, July 08, 2002
From a historical perspective, we will initially examine how semiconductor manufactures have used a number of creative means to optimize and manage their production equipment, control and track production recipes, and prevent serious and often costly excursions in manufacturing. This current state-of-affair will be expanded to provide a glimpse of what the future may hold for assembly equipment as well as semiconductor manufacturers from a progressive and evolutionary perspective.
Fred Rezaei, Intel Corporation

 Factory Automation for Semiconductor Backend Manufacturing: What Was the Advent and What is the Goal? Future Fab Intl. Volume 13, July 08, 2002
In the early 1980s when a young engineer got his first job at any semiconductor factory in Asia, his initial project was usually associated with ‘Factory Automation’. He might be assigned to help a senior engineer who was developing a process with the latest automation equipment. His first automation experience might be integrating a K&S 479 manual wire bonder with a Deltron controller to upgrade the bond placement technique from manual spot light alignment to motorized alignment.
Bo Soon Chang, Cypress Semiconductor, Carl Gamboa, Cypress Semiconductor

 Material Technology Solutions for Lead-free Future Fab Intl. Volume 13, July 08, 2002
The electronics industry is leaning towards SnAgCu family of solders for Lead-free (Pbfree) applications[1,2]. The melting point of these solders is ~350ºC higher than the eutectic SnPb solders, which results in up to 400ºC higher peak reflow temperature. This poses serious technical challenges for the plastic packages used in the electronics industry, which are designed to withstand ~2200ºC process temperature. At the proposed Pb-free process temperatures, packages are challenged to maintain the desired reliability levels.
Vivek Gupta, Intel Corporation, Greg Clemons, Intel Corporation, G Achut Kumar, Intel Corporation, Victoria Mah, Intel Corporation

 Reducing the Cost of Test Using Alternative Techniques and New Architectures Future Fab Intl. Volume 13, July 08, 2002
The drive to reduce the cost of test has been a hot topic of the Semiconductor industry for the past decade. With the demand for higher performance test systems to address newer high speed digital and mixed signal devices came testers with price tags that grew to several million dollars per system. Even before the recent economic downturn, this rising cost for test systems was putting substantial pressure on the profitability of semiconductor manufacturers and the contract test and assembly providers.
Paul Patton, Advantest

 Wafer Level Package for DRAMs: an Opportunity to Revolutionize Backend Manufacturing Future Fab Intl. Volume 13, July 08, 2002
Wafer level package presents a compelling opportunity to revolutionize DRAM backend manufacturing. First, the package is created at wafer level, offering the economies of scale enjoyed in frontend manufacturing. This is especially relevant in the ongoing wafer size conversion from 200mm to 300mm manufacturing. Second, WLP itself can be a critical enabler for wafer level test and burn-in.
Barbera Vasquez, Infineon Technologies AG, Harry Hedler, Infineon Technologies AG, Roland Irsigler, Infineon Technologies AG, Thorsten Meyer, Infineon Technologies AG

 AC Characterization of Digital Integrated Circuits Without Lumped Capacitive Loads Future Fab Intl. Volume 12, February 02, 2002
As a solution to this problem we are proposing performing AC test with no lumped capacitive loads. Loaded characteristics would be determined solely through simulation. To maximize accuracy, the test solution is modeled and used to correlate simulation and test results. The benefits of this approach are improved measurement accuracy, easier implementation of automated test solutions, and a reduction in the need for customized test fixturing. The end result should be a reduction in both cycle time and cost of AC test.
Heather Roberts, Fairchild Semiconductor , William Newberry, Fairchild Semiconductor

 Backend Automation In the Semiconductor Industry Future Fab Intl. Volume 12, February 02, 2002
There have been many productivity drivers that have led to significant levels of automation in the frontend of IC manufacturing[1-5]; however, the backend, which comprises of testing, assembly and packaging (TAP), is yet to witness a similar emphasis on factory-wide automation. In the past, many articles have presented the case for backend automation[6-12].
Alexander H. Slocum, Massachusetts Institute of Technology, Shorya Awtar, Massachusetts Institute of Technology

 Comparison of Final Test Handling Strategies for Massively Parallel Test of Logic Devices Future Fab Intl. Volume 12, February 02, 2002
The typical logic IC is tested multiple times in the manufacturing process to screen out and eliminate defects. The first test is at wafer probe to screen out wafer process defects. Once the device is assembled, it is functionally tested to sort out any remaining defects and ensure that published specifications are met. This last or final test can require multiple insertions at different temperature extremes. Additionally, depending on the end user, the IC may be subjected to burn-in at elevated temperatures for lengthy periods of time, then tested again. As one can see, the test process can be very complex and can add significant cost due to cycle time, inventory, and capital equipment requirements.
Pat Cochran, Motorola Final Manufacturing Technology Center, Goary Kovar, Motorola Final Manufacturing Technology Center, Tim Pham, Motorola Final Manufacturing Technology Center

 New High-Speed, High-Density MEMS-based Probe Technology Future Fab Intl. Volume 12, February 02, 2002
The fundamental challenges associated with achieving a high-parallelism, at-speed test is limited by a host of contactor parameters such as: size, metallurgy, tip design, XY-footprint, test-substrate interconnection, cross-sectional area, overall geometry, spring rate, and fabrication technique. In addition to micro-contactor design, there exists other challenges in the test-substrate or probecard design such as routing style, cross-talk, attention to RF parameters, dielectric constant, loss factors, layer count, and interposer design. Intuitively, these aggressive and necessary requirements will require new approaches to contactor design and system-level probecard design.
Ted Khoury, Advantest

 Removing Test Barriers to Moore's Law Future Fab Intl. Volume 12, February 02, 2002
Moore’s law and its derivatives have been driving our industry for decades, serving not only as an overall goal but also often as a detailed roadmap for scaling.
Mike Mayberry, Intel Corporation

 Thick Photoresist Patterning for Wafer Level Packaging and Bumping Future Fab Intl. Volume 12, February 02, 2002
System integration and packaging are responsible for the functionality, quality and economy of microelectronic products. Due to this fact, advanced packaging technologies are now no longer the niche technologies they used to be in the past. Packaging moved from simple IC housing which protects the sub-micron silicon structures from the outside world to one of the most of the critical enabling technologies for future IC generations. It must satisfy the ever-increasing need for higher electrical performance, further miniaturization, highest reliability, thermal and power management at steady decreasing cost. Packaging and assembly is the bridge between the silicon and the printed wiring board creating the functionality of microelectronic systems.
Martin Töpper, Fraunhofer Institute for Reliability & Microintegration Berlin, Elmar Cullman, Karl Suss, H Reichl, Fraunhofer Institute for Reliability & Microintegration Berlin, Dietrich Tonnies, Karl Suss

 “SECAP” International Advanced Packaging Consortium: Formed to Standardize Process Equipment for Wafer Level Packaging Technologies for 300mm Future Fab Intl. Volume 11, June 29, 2001
Initial participating companies in SECAP include Karl Suss (Germany), Semitool (USA), and Unaxis (Switzerland), all three leading equipment suppliers in photolithography, electroplating and sputtering, as well as Image Technology (USA), a leading producer of large area photomasks (see Figure 1). The Fraunhofer IZM will act as a consultant and technical link to identify specific equipment requirements and will assume the role of the application center for process sequence integration.
Martin Töpper, Fraunhofer Institute for Reliability & Microintegration Berlin, H Reichl, Fraunhofer Institute for Reliability & Microintegration Berlin

 A Revolution in Packaging Technology Future Fab Intl. Volume 11, June 29, 2001
The shift to high gear for the package development world has been driven by several forces: for one, the performance requirements of advanced integrated circuits (ICs) and finished products require increasingly higher levels of I/O density and electrical and thermal performance, and always with constraints of reduced cost. Besides performance drivers, the market has been driven by technology enablers. Today’s IC packages are constructed from an ever-widening palate of materials and processing technologies. The traditional plastic leaded package has been supplemented by multilayer substrates, tape-based packages, die scale packages with redistribution layer, and a whole assortment of new construction concepts.
Neil McLellan, ASAT

 Demonstration and Deployment of a Test Cost Reduction Strategy Using Design-for-Test (DFT) and Wafer Level Burn-In and Test Future Fab Intl. Volume 11, June 29, 2001
Broad implementation of a SOC strategy continues to present new and difficult problems to the overall manufacturing process. SOC devices require the complex integration of several different functional modules; they typically contain a processor core and various types of on-board memory (DRAM, SRAM, Flash), as well as specialized I/O modules.
Tim Cooper, Motorola , Greg Flynn, Motorola , Gans Ganesan, Motorola , Rick Nolan, Motorola , Chau Tran, Motorola

 Elimination of Lead in Semiconductor Packaging Future Fab Intl. Volume 11, June 29, 2001

Carlo Cognetti, STMicroelectronics , Luc Petit, STMicroelectronics

 Grinding and Dicing 300mm Wafers Future Fab Intl. Volume 11, June 29, 2001

Michael Roesner, Infineon Technologies AG, David Wallis, Infineon Technologies AG

 Low Inductance Test Contactors Future Fab Intl. Volume 11, June 29, 2001

Bob Million, Yamaichi Electronics

 Technologies and Trends in Wafer Level Packaging Future Fab Intl. Volume 11, June 29, 2001

TG Tessier, Amkor Technology Inc., C Zwenger, Amkor Technology Inc., Lee Smith, Amkor Technology Inc., H Ueda, Amkor Technology Inc.

 The Decision to Switch Over to Panel Testing: What are the Factors? Future Fab Intl. Volume 11, June 29, 2001

Richard Glover, Fairchild Semiconductor , Robert J Keus, Teradyne, Inc.

 A Question of Picoseconds! Advantest E1381A, an E-Beam Test Solution for 0.13µm Future Fab Intl. Volume 10, July 01, 2001

J Frosien, ACT Advanced Circuit Testing GmbH

 From Flip Chip In Package to a High Reliability Wafer Level Packaging Concept Future Fab Intl. Volume 10, July 01, 2001

Martin Töpper, Fraunhofer Institute for Reliability & Microintegration Berlin, H Reichl, Fraunhofer Institute for Reliability & Microintegration Berlin

 HyperBGA™: a High Performance, Low Stress, Laminate Ball Grid Array Flip Chip Carrier Future Fab Intl. Volume 10, July 01, 2001

DJ Alcoe, IBM Microelectronics Division

 Knowledge-Based Reliability Qualification Testing of Silicon Devices Future Fab Intl. Volume 10, July 01, 2001

DH Eaton, Agilent Technologies, N Durrant, International SEMATECH, SJ Huber, Intel Corporation, R Blish, AMD, N Lycoudes, Motorola

 Underfill Characterization for Flip Chip BGA Featuring Use of a Rigid Substrate Future Fab Intl. Volume 10, July 01, 2001

Kunio Sakamoto, Texas Instruments Incorporated

 Advancements in Stacked Chip Scale Packaging (S-CSP) Provides System-in-a-Package Functionality for Wireless and Handheld Applications Future Fab Intl. Volume 9, January 07, 2000

Morihiro Kada, Sharp Corporation, Lee Smith, Amkor Technology Inc.

 Chip Scale Package Burn-In Socket Technology as Pitches Move 0.5mm Future Fab Intl. Volume 9, January 07, 2000

James Forster, Texas Instruments Incorporated

 Design for Reliability Methodology for Package Development Future Fab Intl. Volume 9, January 07, 2000

Enrico Garcia, Intel Corporation, Timothy Rothman, Intel Corporation

 Evolution in System Integration Packaging Future Fab Intl. Volume 9, January 07, 2000

Toshio Hamano, Fujitsu Corporation

 Lead-Free Electronics: Searching for a Lead Replacement Future Fab Intl. Volume 9, January 07, 2000

Slaman Akram, Micron Technology Inc

 On-line Monitoring of the Dicing Process Future Fab Intl. Volume 9, January 07, 2000

Iian Weisshaus, Kulicke & Soffa Industries, Gil Weisman, Kulicke & Soffa Industries

 From Wafers to Chips: The Challenge of Process Control in Dicing Future Fab Intl. Volume 8, July 01, 2000

Werner Kröninger, Infineon Technologies AG, Ludwig Schneider, Infineon Technologies AG

 Getting the Most from Your Handler Future Fab Intl. Volume 8, July 01, 2000

Jack Kessler, Concepts Unlimited

 High Pin Count Power Package for High Current, High Temperature Automotive Applications Future Fab Intl. Volume 8, July 01, 2000

Paolo Casati, STMicroelectronics , Carlo Passagrilli, STMicroelectronics , Roberto Tiziani, STMicroelectronics

 IBM Chip Packaging Roadmap Future Fab Intl. Volume 8, July 01, 2000

Eric Laine, IBM, Patrick O'Leary, IBM

 Reducing MEMS Product Development and Commercialization Time Future Fab Intl. Volume 8, July 01, 2000

Fariborz Maseeh, IntelliSense Corporation

 Socket Contacting Technology Trends for Flip Chip and Chip Scale Packages Future Fab Intl. Volume 8, July 01, 2000

Slaman Akram, Micron Technology Inc