In this issue:
Future Visions & Current Concerns
 INTRODUCTION: Future Visions and Current :: Download the new issue now!
Over the last several years, our industry has been significantly transformed. The way we now do business is dramatically different than the way we did business 20 or 30 years ago.
Stephen J. Buffat, Lockheed Martin Corporation
Avoid Common Intellectual Property Pitfalls :: Download the new issue now!
An article listing some common intellectual property pitfalls encountered by semiconductor companies and provides guidance on how those mistakes can be avoided.
Steven E. Ross, Gardere Wynne Sewell LLP, Karl L. Larson, Gardere Wynne Sewell LLP
Brokering Digital CMOS Technology :: Download the new issue now!
A paper that explains why there is a growing knowledge gap between CMOS’ producers and consumers, and what can be done to bridge it.
Phillip Christie, NXP Semiconductors
New Technologies & Device Structures
INTRODUCTION: New Technologies & Device Structures :: Download the new issue now!
Companies, research centers and universities active in microelectronics are all facing the headwinds of a – to put it mildly – challenging operating environment. Most believe that the way forward is in relentless innovation – innovation that is taking into account the challenges of the 21st century: the quest for sustainable energy generation, affordable and better healthcare, and an information and communication infrastructure for everyone.
Lode Lauwers, IMEC
SiGe MEMS Technology :: Download the new issue now!
A paper that discusses why poly-SiGe post-processing might ultimately enable the creation of highly integrated miniature systems with multiple packaged sensors and actuators post-processed on a single chip.
Ann Witvrouw, IMEC, Simone Severi, IMEC, Philippe Helin, IMEC, Luc Haspeslagh, IMEC
New Technology and Collaboration Models for Sustainable Profitability :: Download the new issue now!
Why costs of semiconductor innovation will continue to skyrocket, why current development methods and collaboration models do not go far enough, and how to get collaboration models that will provide mutual incentives for success across the supply chain.
Rebecca Mih, Intermolecular Inc., Sean Barstow, Intermolecular Inc.
Design Implementation & Process Integration
INTRODUCTION: Design Implementation & Process Integration :: Download the new issue now!
Today there is no limitation in the demands to integrate more and more functions on a semiconductor chip. Moore’s Law has supported this advance for decades.
Kazu Yamada, NEC Electronics America, Inc.
Simulation to the Rescue of ITRS Roadmap Complexity :: Download the new issue now!
Today’s MOSFETs look like distant cousins of the MOSFETs we studied at university
a mere decade ago. Far from simple scaled versions of previous designs,
they feature silicon germanium embedded in raised source and drain regions, high-k
gate dielectrics and, in a curious revivalist twist, metal gates.
Synopsys Business Development, Synopsys
Approaching 2X Technology Node(s): Lithography, OPC and DFM Options for Manufacturable Designs :: Download the new issue now!
A look at approaches that will allow the realization of 2X technology node devices with reasonable yield and cost.
Soichi Inoue, Toshiba Corporation
3D Stacked Silicon Using Through Silicon Via :: Download the new issue now!
A presentation of alternative 3D technologies, emphasizing the benefits of through silicon via, as well as prediction of future trends of 3D regarding partitioning, placement and stack growth.
Roger Carpenter, Javelin Design Automation
Manufacturing, Systems & Software
INTRODUCTION: Manufacturing Systems & Software :: Download the new issue now!
The challenges facing the semiconductor industry are considerable and include both the technological and the economic. As has always been the case, the two are intertwined.
Thomas Sonderman, AMD
The Challenges and Opportunities of Change in the Equipment Industry :: Download the new issue now!
An exploration of the pros and cons of standardizing the platforms for vacuum process tools that also identifies a solution beneficial to OEMs as well as IDMs.
Larry Dulmage, Crossing Automation, Larry Wise, Crossing Automation
Front End of Line
INTRODUCTION: Front End of Line :: Download the new issue now!
Spring is here. In our fond memories of springs past, designers would pull out their Moore’s Law calculators, with their single “0.7x” button, to define patterning requirements for the next node. Stepper designers would grow the lens numerical aperture to an “impossible” 0.54, process engineers would tweak the resist and etch processes, and the job would be done.
Janice Golda, Intel Corporation
INTRODUCTION: Front End of Line :: Download the new issue now!
Continued dimensional scaling will require either EUV lithography (very promising, yet still very challenging) or getting more from the available optical scanners, most likely with multiple exposures.
John Warlaumont, SEMATECH
Build Your Future With Nikon :: Download the new issue now!
From high-throughput i-line steppers to advanced immersion ArF scanners
for 32nm applications and beyond, Nikon delivers superior performance with the
lowest cost of ownership and the most comprehensive customer support of any
manufacturer.
Nikon Business Development, Nikon
Double Patterning Lithography: Reducing the Cost :: Download the new issue now!
A paper describing process flows, steps and materials, regarding cost, line roughness, overlay and critical dimension uniformity regarding double patterning lithography for the 32nm technology node.
Andy Miller, IMEC, Jan Provoost, IMEC, Mireille Maenhoudt, IMEC
An Engineering Model of the C4F8/O2/Ar Chemistry in the Dry Etching of SiO2 :: Download the new issue now!
A presentation of a zero-dimensional dry etching model that can link the average etching performance to the main engineering/equipment parameters, particularly one that enables the calculation of the polymer coverage as a function of the gas flow.
Giuseppe Garozzo, Numonyx Development Center, Italy , Antonino La Magna, CNR-IMM, Italy , Stefano Colombo, ST-Microelectronics, Italy
Back End of Line
INTRODUCTION: Back End of Line :: Download the new issue now!
Two scaling trends have fueled the last several decades of the information age, which have followed a phenomenal, super-exponential growth in digital computing power per unit cost, per unit device area and per unit calculation time. These are Moore’s Law and Dennard Scaling, which respectively describe increases in integrated circuit density and CMOS circuit speed with continued miniaturization of the circuit elements. Both of these trends are beginning to saturate, as they are being impacted by several physical and practical barriers.
Dan Edelstein, IBM’s T.J. Watson Research Center
Removing Heat From 3D Stacked Chips :: Download the new issue now!
An article that presents a microchannel cooling technology for 3D stacked ships.
Deepak C. Sekar, Sandisk Corp., Calvin R. King, Georgia Institute of Technology, Bing Dang, IBM’s T.J. Watson Research Center, Muhannad S. Bakir, Georgia Institute of Technology, James D. Meindl, Georgia Institute of Technology
Wafer Fab & Packaging Integration
INTRODUCTION: Wafer Fab & Packaging Integration :: Download the new issue now!
“There is only an inch of water needed beyond the bottom of a ship.” These words could be translated into thin silicon technology: “There is only a micron of silicon needed beyond the active layers.”
Peter Ramm, Fraunhofer IZM, Munich
Electrostatic Carrier Technique for Thin Wafer Processing :: Download the new issue now!
A paper that describes a new carrier technique being developed that uses electrostatic forces for reversible attachment of thin and fragile wafers to a rigid support substrate, a patented new concept called mobile electrostatic carrier.
Christof Landesberger, Fraunhofer Institute for Reliability and Microintegration IZM, Robert Wieland, Fraunhofer Institute for Reliability and Microintegration IZM, Peter Ramm, Fraunhofer IZM, Munich, Karlheinz Bock, Fraunhofer Institute for Reliability and Microintegration IZM
Assembly Test & Packaging Technologies
INTRODUCTION: Assembly Test & Packaging Technologies :: Download the new issue now!
Many companies in the industry are carefully husbanding their resources for investment in research and development, in preparation for inevitable economic upturn and market resurgence. In recent years, there have been great advancements in innovation and invention of electronics products, largely driven by the imperatives of the expanding consumer market.
William (Bill) T. Chen, ASE (U.S.) Inc.
For SIPs, Concurrent RF Testing Delivers Advantages in Cost-of-Test and Quality of Results :: Download the new issue now!
This paper that describes what RF testing is and why it matters also explains why the benefits include more-accurate and realistic testing, along with higher throughput.
Keith Schaub, Advantest America Corporation
|
