In this issue:
Future Visions & Current Concerns
 INTRODUCTION: Future Visions & Current Concerns :: Download the new issue now!
To maintain the growth and profitability
of our industry, miniaturization
through technological advances and
increasing wafer size are necessary to
continue to reduce fabrication costs.
Stephen J. Buffat, SCP Global Technologies
The Emergence of Bionanotechnology, Part I :: Download the new issue now!
As the nanoelectronics industry has executed aggressively to the International Technology Roadmap for Semiconductors, it has pushed device dimensions past cells, bacteria and viruses, and reached the size of larger biological molecules. Concomitant with this structural trend, biology and medicine have begun to integrate the technologies and techniques of micro- and nanofabrication into new instruments, devices and perhaps most intriguing, chip-based diagnostic techniques. Such developments as subminiature cameras, probes and implanted RFID use CMOS and MEMs chips systems for medical applications. However, in biochips, novel systems and materials are emerging that directly interact with biochemistry, and as devices approach the size of biomolecules themselves, new opportunities are emerging to harness chip-based technology for biochemistry and medicine and other applications with dramatically increasing levels of integration.
Rob Meagley, ONE Nanotechnologies, LLC
Contemplating 450 mm :: Download the new issue now!
The semiconductor industry’s introduction of 300 mm wafers required addressing some significant manufacturing challenges. The industry is now contemplating 450 mm wafers. Respondents to a survey conducted by Wright Williams & Kelly, Inc. (WWK) in April of 2007 suggested that the challenges to 450 mm wafer introduction may be economically insurmountable. WWK followed up on the survey results by using economic models to compare profitability of 300 mm and 450 mm wafer fabs based on current manufacturing and economic trends. This article will look at some of the challenges that 300 mm manufacturing overcame and some of the anticipated challenges that 450 mm manufacturing must address.
Daren Dance, Wright Williams & Kelly, Inc., David Jimenez, Wright Williams & Kelly, Inc.
New Technologies & Device Structures
INTRODUCTION: New Technologies & Device Structures :: Download the new issue now!
In this issue of Future Fab International,
you will find some exciting reports on innovative
ways of producing nanophotonics
and also new results on organic-based
electronics.
cal buffering. Stay tuned for the follow-up
article on how to bridge between research
and commercialization.
Researchers from the University of Texas
Paolo Gargini, Intel Corporation
INTRODUCTION: New Technologies & Device Structures :: Download the new issue now!
Research on new technologies concentrates
on more than just finding new
processes and materials for the sub-32nm
nodes. The two papers in this section bear
witness to an intense interest in alternative
devices, using, for example, light; or in alternative
materials, as used in, for example,
organic electronics. The rationale behind
this research is not only traditional scaling,
but finding low-cost, manufacturable solutions
for specific needs and applications.
Lode Lauwers, IMEC
Silicon Nanophotonics :: Download the new issue now!
Silicon photonics builds on the momentum of silicon electronics to deliver to photonic integration what was lacking: a generic integration platform. Silicon-based nanophotonic ICs tremendously increase the integration scale, and the functionality per chip, compared with their counterparts in other material systems (glass, III-V semiconductor, etc.). This will drive adoption of photonic integration by a wide range of volume applications with increasing requirements in size, weight and power consumption.
Pieter Dumon, Ghent University – IMEC, Wim Bogaerts, Ghent University – IMEC, Alexei Tchelnokov, CEA-Leti, Jean-Marc Fedeli, CEA-Leti, Roel Baets, Ghent University – IMEC
Organic-Based Electronic Devices and Circuits :: Download the new issue now!
In this article, we review recent results obtained in our laboratory on organic semiconductor-based devices and circuits. Manufacturable photolithography-based fabrication techniques were implemented to fabricate capacitors, Schottky diodes, organic thin film transistors (OTFTs), and several analog and logic circuits. All processes were performed below 120°C, which makes these integrated devices suitable for low-temperature flexible circuit applications. Specifically, our devices have been integrated to fabricate rectifiers, amplifiers, ring oscillators, current mirrors, matched pairs, and other circuits. Good performance is obtained for the single-stage rectifiers, and acceptable performance is obtained for integrated amplifiers, matching pairs and ring oscillators. The OTFTs are all based on pentacene as organic semiconductor, while the Schottky diodes are based on copper phthalocyanine (CuPc).
Husam N. Alshareef, Texas Instruments Incorporated, Manuel Quevedo-Lopez, University of Texas at Dallas, Srinivas Gowrisanker, University of Texas at Dallas, Yuming Ai, University of Texas at Dallas, Bruce Gnade, University of Texas at Dallas
Design Implementation & Process Integration
INTRODUCTION: Design Implementation & Process Integration :: Download the new issue now!
As old-timers know, mask making used
to be a “no-brainer” and a straightforward
process in IC manufacturing, up until
130nm. This last stage of design used to
take no longer than a few days and cost a
fraction of overall design and manufacturing
expenses. However, when engineers
began attempting to design geometries
smaller than 100nm on silicon – with a 248
or 193nm wavelength – making masks
became the equivalent of using an axe to
craft fine pieces of woodwork! Another limitation
for Moore’s law!
Kazu Yamada, NEC Electronics America, Inc.
It Takes a Village to Reduce Mask Costs :: Download the new issue now!
There is an old proverb that says, “It takes a village to raise a child.” The gist is that it takes a collaborative effort among different players to make a difference. Three very different companies from the design, photo-mask and equipment spaces are applying the proverb to create a virtual village to tackle costs.
Mitchell Heins, Pyxis Technology, Inc., Christopher Progler, Photronics Inc., Venu Vellanki, KLA-Tencor
eDFM – Not “If” It Will Print, But “How”? :: Download the new issue now!
Electrical Design for Manufacturing (eDFM) is an emerging field of technology that asserts to predict how a circuit will behave as modified by distortions in the manufacturing process. While the original work in DFM was centered on lithography, eDFM goes further to predict and optimize the effects on power and performance of chip designs. This article provides an introduction to eDFM and an abbreviated canvas of the available tools in the market.
Randy Smith, Randysan Consulting
Manufacturing, Systems & Software
INTRODUCTION: Manufacturing, Systems & Software :: Download the new issue now!
So as the industry debate over a
potential transition to 450 mm wafers
intensifies, it is especially fitting that
both papers in this section look at ways
of improving factory performance at our
current technology nodes. As we saw in
the mid-90s, some of the operational
improvements that were achieved in
anticipation of the automation requirements
for 300 mm actually reduced the
urgency of the transition itself (not to
mention a couple of years of industry
down cycle). Sound familiar?
Alan Weber, Alan Weber and Associates
Modeling Semiconductor Factories for Equipment and Cycle Time Reduction Opportunities, Part II :: Download the new issue now!
International SEMATECH Manufacturing Initiative’s (ISMI’s) Small Carrier Capacity Task Force began with the purpose of investigating potential cycle time reductions when smaller carriers with a 12-wafer capacity are used. Other purposes included finding cycle time benefits while employing current 25-wafer carriers. This analysis quantifies the potential cycle time benefits to be achieved by implementing equipment improvements, replacing batch equipment with single-wafer processing tools, and adjusting lot cascade lengths.
Emrah Zarifoglu, University of Texas at Austin, Robert Wright, International SEMATECH Manufacturing Initiative (ISMI), Chad Bubela, Texas State University, Joey Preece, Texas State University
What Are the Alternatives to 450 mm Wafers? :: Download the new issue now!
Questions have been raised with regard to larger wafer diameters. In this paper, obstacles faced by 450 mm wafers are summarized. Two alternatives to larger wafers are proposed. The first is to employ methods available through lean manufacturing and manufacturing science to improve factory performance in 300 mm or 200 mm fabs. The second proposal is the consideration of efforts toward achievement of the “ideal factory” via single chip processing, or SCP.
James Ignizio, Manufacturing Science Consultant
Front End of Line
INTRODUCTION: Front End of Line :: Download the new issue now!
The continued march to shrink feature
sizes to double density every two years has
enabled the industry to realize Moore’s law.
As feature dimensions continue to scale, a
number of previously insignificant factors
are becoming increasingly important to
control in order to deliver high product
performance at high yields. Keeping reticles
defect free over their life cycle has always
been essential to delivering high yields, as a
single printable reticle defect can affect
every die on every wafer if not caught. In
this issue of Future Fab International, you
will find a thought-provoking paper on a
new consideration for managing reticles
over the reticle life cycle.
Janice Golda, Intel Corporation
EFM: A Pernicious Threat to Reticles – Exposed :: Download the new issue now!
In Issue 22, a brief overview was given of the changing nature of reticle electrostatic damage, and the consequences for semiconductor fabs were discussed. The conclusions in that review were based on the interpretation of many pieces of evidence taken from different sources, but the risk assessment was empirical, so has not yet been widely accepted. This article presents new data from an experiment that was designed to quantify the damage effects under closely controlled conditions.
Gavin Rider, Microtome
When Other Graphite Materials Hit the Wall, Poco Graphite Breaks Through :: Download the new issue now!
Poco Graphite manufactures specialty
graphites and silicon carbide with
custom machining capabilities for
OEMs and fabs.
Poco Graphite, Inc.
Ultrathin Barrier/Seed Layers: Challenges of Scaling for Future Copper Interconnect :: Download the new issue now!
This article explores the scaling trends and subsequent process technology advances in ultrathin barrier/seed layers for Cu interconnect.
Jeff Catlin, ATMI, Inc., Jeff Roeder, ATMI, Inc., Bryan C. Hendrix, ATMI, Inc.
Back End of Line
INTRODUCTION: Back End of Line :: Download the new issue now!
The Interconnect low dielectric constant
predictions incorporated in the ITRS roadmap
are a good example of overestimation
of the pace of technology change in our
industry. The predictions of the pace of
change of low dielectric constant (low-k)
materials were overly optimistic and were
revised many times as different process
technologies were evaluated for high-volume
production.
Dr Jeffrey T Wetzel, SVTC LLC/ATDF, Inc
Metrology, Inspection & Failure Analysis
INTRODUCTION: Metrology, Inspection & Failure Analysis :: Download the new issue now!
“The need for speed” is not just my
nephew’s favorite Playstation game; nor is
it a clause taken directly from the introduction
of one of the papers. The “need
for speed” is the imperative of our world,
from its beginning.
Davide A. Lodi, Numonyx
Integrated Metrology Role in Improving Fab Productivity and CoO :: Download the new issue now!
Using integrated metrology (IM) in semiconductor wafer processing can benefit wafer fabs in many ways. This article outlines the IM concept, discusses the requirements for a successful integrated metrology tool and outlines the benefits of using IM in terms of improved fab yield, improved process control, automated material handling system (AHMS) and metrology cost reduction, and fab cycle-time improvement.
Ira Naot, Tevet Process Control Technologies, Robert Mohondro, Tevet Process Control Technologies
Industry Sub-Cycles Spark Diversity :: Download the new issue now!
Jordan Valley’s novel, noncontacting,
nondestructive X-ray technologies enable
the power and flexibility to develop current- and
next-generation materials and processes
across a wide variety of applications.
Jordan Valley Semiconductors, Inc.
A New Photo-Reflectance Approach to USJ and Strain Metrology :: Download the new issue now!
This paper is the first of a two-part series which describes the use of a new photo-reflectance technique for the in-line characterization of strain and USJ dopant activation in advanced FEOL processing.
Will Chism, Xitronix Corporation, Victor Vartanian, International SEMATECH Manufacturing Initiative
Wafer Fab & Packaging Integration
INTRODUCTION: Wafer Fab & Packaging Integration :: Download the new issue now!
3D system integration is a promising
and more and more accepted approach
for fabrication of high-performance
applications as advanced processors,
memory stacks and image sensors, as
well as so-called “More than Moore”
applications, focusing on smart system
integration rather than transistor density
(e.g., wireless sensor systems, “e-CUBES”).
Peter Ramm, Fraunhofer IZM, Munich
Modeling and Simulation for 3D Design Support :: Download the new issue now!
Due to high-integration density, the influence of manufacturing technologies on the system behavior must be considered in the design process of 3D systems. Therefore, information from different physical domains must be provided to designers. The variety of structures and physical effects requires efficient modeling approaches and simulation algorithms. The following describes a modular approach which covers detailed analysis with PDE solvers and more abstract behavioral modeling.
Peter Schneider, Fraunhofer Institute for Integrated Circuits, Division Design Automation, Sven Reitz, Fraunhofer Institute for Integrated Circuits, Division Design Automation, Roland Martin, Fraunhofer Institute for Integrated Circuits, Division Design Automation, Jörn Stolle, Fraunhofer Institute for Integrated Circuits, Division Design Automation
Perfect Chips: Chip-Side-Wall Stress Relief Boosts Stability :: Download the new issue now!
An increase of up to 500 percent die strength is achieved applying the new chip-side healing technology introduced by PVA TePla as a stress relief step after blade or laser dicing, in addition to the conventional wafer-level back-side stress relief after grinding. Hence, after the chip-side healing, the complete five-side restoration of silicon lattice integrity for each single chip can be achieved – a must for any ultrathin die assembled in advanced 3D packages. The methods and results are presented herein.
Peter Heinze, PVA TePla AG, Martin Amberger, PVA TePla AG, Therese Chabert, PVA TePla AG
Assembly, Test & Packaging Technologies
INTRODUCTION: Assembly, Test & Packaging Technologies :: Download the new issue now!
New technologies are the lifeblood of
the electronics industry. Engineers with
their “out of the box” thinking are working
on leading-edge pathfinding projects
that create significant changes in the way
the industry does things. Revolutionary
advances change the direction of a technology,
while evolutionary advances
refine the current state of the art to a
better level.
Steve W. Greathouse, Plexus Corporation
The Occam Process: Solderless Assembly and Interconnection of Electronic Packages :: Download the new issue now!
This article will describe details of what has come to be known as the Occam Process, so named to honor the 14th-century English philosopher and logician, William of Occam, whose rigorous thinking and arguments favored and encouraged the finding of the simplest possible solution to every problem.
Joseph Fjelstad, Verdant Electronics
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