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July 2013 Issue:

Future Visions & Current Concerns

 Introduction  Download the new issue now!
About every 10 years, the semiconductor industry reinvents itself in order to make progress. In this issue of Future Fab International, you will find two significant examples of this innovation process.
Paolo A. Gargini, International Technology Roadmap for Semiconductors (ITRS)

 Chapter Article Sponsor  Download the new issue now!
Hitachi’s renowned etch technology, paired with unmatched service and support, provides customers with etch solutions to meet their stringent development and production requirements.
Hitachi High Technologies America, Inc.

 Facility Considerations for the 450 mm Transition  Download the new issue now!
Making 450 mm a reality is not only a monumental task from a technical and manufacturing standpoint, but as we consider the facility infrastructure, it becomes apparent that merely scaling the new facility is not a practical option. The size of the 450 mm facility infrastructure and associated utility consumption projections will simply exceed affordability realities or resource constraints. These roadblocks can be addressed only through solutions developed in collaboration with facility experts across the entire supply chain. M+W Group, as a leading design-builder of technical facilities, in consultation with Global 450 mm Consortium (G450C), is coordinating with select semiconductor facility companies around the globe to bring their collective expertise to bear on the most pressing facility issues. These collective companies form the Facility 450 mm Consortium (F450C).
Allen Ware, M+W U.S., Inc. – A Company of the M+W Group, Don Yeaman, M+W U.S., Inc. – A Company of the M+W Group

 Thought Leadership Profile  Download the new issue now!
A revolution in thinking is needed at every level of the process before it is too late. The handbook already exists; all that’s missing is the call to action. Consider this the first call.
Total Facility Solutions Business Development, Total Facility Solutions

 Europe’s Next Wave of Innovation  Download the new issue now!
Nanoelectronics is an engine of innovation, addressing some of the key challenges of our society. It fuels innovation in many industry sectors, which are all important for Europe. But to sustain Europe’s growth, a powerful and effective R&D engine is needed. This will make Europe a competitive region for R&D and manufacturing of nanoelectronics, but also for the value chains that build on it, such as automotive, communication, health care or energy. Therefore, we are very excited that the European Commission has identified nanoelectronics as a key enabling technology (KET) essential for the future of Europe.
Anne Van den Bosch, imec

New Technologies & Device Structures

 Introduction  Download the new issue now!
As Future Fab wraps up a distinguished run of service to the international semiconductor community, I would like to take this opportunity to thank my colleagues for offering concise, timely and relevant technology updates and contributions through this publication. Like the phoenix, I trust that new publication opportunities will arise from these ashes that will be well positioned to catch and ride the next tidal waves of emerging technologies.
Daniel J.C. Herr, Joint School of Nanoscience and Nanoengineering/UNC−Greensboro

 Advancing the Use of Carbon Nanotubes for Future Chip Manufacturing  Download the new issue now!
In the race to produce ever-smaller and -faster computer chips, carbon nanotubes (CNT) could play an important role. Based on their electrical characteristics, bundles of CNTs would be excellent candidates to replace the copper interconnecting wires of today’s chips.
Jan Provoost, imec

Chip Architecture & Integration

 Introduction  Download the new issue now!
For nearly 50 years, Moore’s Law has reliably predicted the doubling of transistors on an integrated circuit every two years. However, in recent years, whispers that “Moore’s Law is dead” abound, as keeping on the technology treadmill bumps up against the limits of physics, economic viability, and the very nature of the application space for semiconductors in a post-PC world.
Warren Savage, IPextreme

 Interconnect Issues: History and Future Prospects, Part 2  Download the new issue now!
The research pipeline of the semiconductor industry involves increasingly radical potential solutions to carry technology advancement through dimensional scaling to beyond-conventional CMOS. Many logic devices are under investigation to extend Moore’s Law to beyond the year 2020. These logic devices differ in structure and operating principles, and include various physical quantities that may be used for encoding information, such as charge, electric dipole, magnetic dipole (spin), orbital state, mechanical position, light intensity, etc. However, any device technology that offers advantages in performance, power dissipation or ease in dimensional scaling will have to be complemented with an interconnect technology that offers similar trades to avoid major bottlenecks due to interconnects. Various carbon-based interconnects were shown to have comparable or better performance compared to Cu/low-k in terms of both resistance-capacitance (rc) product and energy-delay-product.
Ahmet Ceyhan, Georgia Institute of Technology, Azad Naeemi, Georgia Institute of Technology

Lithography Landscape

 Introduction  Download the new issue now!
In this edition of Future Fab, Yayi Wei and David Cho of GLOBALFOUNDRIES examine the conundrum facing lithographers seeking patterning solutions for the 10 nm node, as the technical and cost challenges of extending 1.35NA 193 nm immersion patterning become more daunting.
Janice M. Golda, Intel Corporation

 Thought Leadership Profile  Download the new issue now!
In order for semiconductor manufacturers to maintain production timelines, extension of 193 nm lithography is vital.
Nikon Corporation

 An Analysis of Lithography Solutions to 10 nm Logic Node and Beyond  Download the new issue now!
According to the ITRS, the risk production of 10 nm logic devices is scheduled in 2015. Ten nm logic device requires a critical poly pitch of 64 nm and first metal half-pitch of 24 nm. An overlay control of < 5 nm (3) and critical-dimension uniformity control of < 2.2 nm (3) are required in lithographic process. Assuming 0.7x scaling per node, 7 nm node will require a CPP of 45 nm, first metal half-pitch of 20 nm, overlay control of < 3.5 nm and CDU control of < 1.5 nm.

Metrology, Inspection & Failure Analysis

 Introduction  Download the new issue now!
Amid the continued advances of 3D interconnect technology, related improvements in the associated metrology have become ever-more critical.
Alain C. Diebold, College of Nanoscale Science and Engineering, University at Albany

 TSV Metrology and Inspection Challenges for 3D Heterogeneous Integration  Download the new issue now!
3D heterogeneous is receiving more and more attention, as it will consolidate market demands for more performance and more functionality in future devices. However, before its complete implementation in high-volume production, several challenges remain, some of them related to the associated metrology and inspection. This paper will focus on those for TSV technology in terms of etching; isolation; metal filling and reveal; vias process steps.
Carlos Beitia, CEA-Leti, Vanessa Monier, CEA-Leti


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