In this issue:
Special Introduction
 Special Introduction: Download the new issue now!
Please find the 2011 latest edition of the fully revised ITRS as it is regularly published on every odd year. Since the 2011 ITRS is a dynamic document, you will find many exciting new ideas and improvements as compared with the 2009 ITRS version.
Paolo Gargini, Intel Corporation
Future Visions & Current Concerns
Introduction: Download the new issue now!
The Environment, Safety and Health (ESH) Chapter is unique in the ITRS Roadmap. While the Roadmap is by intent a technology-focused document, the ESH section must necessarily also address policy and regulatory issues. This was first explicitly recognized in the 2009 Roadmap, and is further extended in the 2011 ESH Chapter.
Gilbert Declerck, imec
Environment, Safety & Health: Download the new issue now!
The 2011 ESH section of the Roadmap continues to reflect the fact that the principles of successful ESH program execution remain largely independent of the specific technology thrust advances to which they are applied. Thus, many ESH Roadmap elements, such as the Difficult Challenges and the Technology Requirements, bear strong similarities to those in the 2009 Roadmap.
Leo Kenny, Intel Corporation
RF and A/MS Technologies: Download the new issue now!
Radio frequency and analog/mixed-signal (RF and A/MS) technologies are essential and critical technologies for the rapidly diversifying semiconductor market that comprises many more applications than the wireless and wire-line communications applications covered in previous editions of this chapter. We describe the requisite technology elements for circuits used in not only wireless and wire-line communications but also new for this year, in low-frequency analog applications such as power management and display drivers.
Herbert S. Bennett, National Institute of Standards and Technology, John J. Pekarik, International Business Machines Corporation
New Technologies & Device Structures
Introduction: Download the new issue now!
Transitions within the ITRS could fundamentally impact its scope and approaches to high-volume nanomanufacturing.
Daniel J.C. Herr, University of North Carolina at Greensboro
Chapter Article Sponsor: memsstar: Download the new issue now!
memsstar Limited is a leading provider of deposition and etch equipment enabling technology solutions to micro-electrical mechanical systems (MEMS) manufacturers.
memsstar Business Development, memsstar
MEMS: Download the new issue now!
Micro-electromechanical systems are devices that are fabricated using techniques similar to those used for integrated circuits to create micrometer-sized mechanical structures (suspended bridges, cantilevers, membranes, fluid channels, etc.) that are often integrated with analog and digital circuitry. MEMS can act as sensors, receiving information from their environment, or as actuators, responding to a decision from the control system to change the environment. The ITRS has organized a MEMS Technology Working Group that has developed a new chapter on MEMS for its 2011 report. The report focuses on MEMS technologies associated with mobile Internet devices, such as smartphone and tablet computers. These applications represent the fastest-growing segment in MEMS manufacturing, according to 2011 market forecasts by iSuppli, Yole Developpement and SEMI. The leading MEMS devices used in mobile Internet devices studied in this report are accelerometers and gyroscopes, microphones and RF MEMS, including resonators, varactors and switches. The report also reviews emerging MEMS applications, including optical filters, pico-projectors, the electronic nose, microspeakers and ultrasound devices.
Michael Gaitan, NIST, Paul Tsai, TSMC , Philippe Robert, CEA-Leti
Chapter Article Sponsor: SAFC: Download the new issue now!
SAFC Hitech delivers unmatched expertise in both advanced chemistry and process technology for the semiconductor industry.
SAFC Hitech
Emerging Research Devices: Download the new issue now!
The 2011 Emerging Research Devices (ERD) Chapter provides an ITRS perspective on emerging research memory, logic and information processing device technologies, and serves as a bridge between CMOS and the realm of nanoelectronics beyond the end of CMOS dimensional and equivalent functional scaling. The Chapter further addresses memory and information processing nanoarchitectures related to and made possible by emerging research devices. This paper addresses the highlights of the 2011 ERD Chapter, with particular focus on technology transitions from ERD to other Technical Working Groups closer to technology commercialization. Expanding the chapter this year, new “Beyond CMOS” device structures and architectures also are addressed.
James A. Hutchby, Semiconductor Research Corporation
Chapter Article Sponsor: MEMC: Download the new issue now!
Our semiconductor wafer products are the foundation for the technologies that entertain us, educate us and connect us to each other.
MEMC Electronic Materials, Inc.
Emerging Research Materials: Download the new issue now!
During the past decade, new materials were integrated into the semiconductor fabrication process to overcome limitations of conventional materials’ ability to meet increasing integrated circuit technology performance requirements. In 2007, the Emerging Research Materials (ERM) Technology Working Group (TWG) was launched to identify and track research materials that had the potential to provide solutions to strategic ITRS difficult challenges across the technology-related TWGs. The 2011 ITRS ERM chapter continues to assess the viability of ERM to meet specific TWG-identified projected requirements and application needs, where current materials may not suffice.
Michael Garner, Intel Corporation, Daniel Herr, Semiconductor Research Corporation, Hiro Akinaga, National Institute of Advance Industrial Science and Technology (AIST), Paul Zimmerman, Intel Corporation
Design Implementation & Process Integration
Introduction: Download the new issue now!
One characteristic of a roadmap is that, while ever advancing, its “depth of field” remains essentially constant. Thanks to persistent research investments, items that were previously fuzzy come into clear focus, new items requiring focus emerge (with some blur), and completed items drop off behind us. This premise is amply demonstrated by the two papers in this section.
Steven Schulz, Silicon Integration Initiative, Inc.
Design and System Drivers: Download the new issue now!
The Design and System Drivers Chapters of the ITRS Roadmap provide a view into critical design technology challenges and required solutions across various market domains and abstraction levels. The solutions are fundamental to improved tools and methodologies that will enable the development of future electronic products. The Design Technology Roadmap encompasses every pre-manufacturing aspect of developing a semiconductor product, and sets out a 15-year path of improvements needed to sustain the industry’s amazing pace. For many years, the scaling of electronic product value has been only partly based on manufacturing improvements. Design technology has become a key enabler of the overall semiconductor Roadmap, and is increasingly aligned and mutually dependent with the manufacturing and device aspects of the ITRS.
Juan-Antonio Carballo, NetLogic Microsystems , Andrew B. Kahng, University of California, San Diego
Modeling & Simulation: Download the new issue now!
Modeling & Simulation shares the same starting point with most other areas of the ITRS: the physical understanding of equipment, processes, devices, circuits and systems that is the prerequisite for the development of new technologies and advanced solutions. The specific feature of Modeling & Simulation is then to extract from this knowledge physical models – which predominantly means (partial) differential equations together with their parameters – that describe device fabrication and/or device, circuit and system properties. These models are then implemented and used in (numerical) simulation tools.
Jürgen Lorenz, Fraunhofer Institute for Integrated Systems and Device Technology (IISB)
Manufacturing: Fab, Systems & Software
Introduction: Download the new issue now!
The empirical law known as Moore’s Law, in the medium- and long-term vision, is a common and key reference in the semiconductor field. The important role of our professionals is to pay attention to today’s challenges but also to emerging trends and the implications for the future of innovation.
Giuseppe Fazio, Micron
Process Integration, Devices, & Structures: Download the new issue now!
The Process Integration, Devices, and Structures (PIDS) chapter deals with the main IC devices and structures, the overall IC process-flow integration and the reliability trade-offs associated with new options. Physical and electrical requirements and characteristics are emphasized within PIDS. Parameters such as physical dimensions and key device electrical parameters including performance, leakage and reliability criteria are considered. The main goals of the ITRS include identifying key technical requirements and challenges critical to sustaining the historical scaling of CMOS technology per Moore’s Law and stimulating the needed research and development to meet the key challenges. The chapter is divided into the following major sections: logic, DRAM, non-volatile memory (NVM) and reliability.
Kwok Ng, Semiconductor Research Corporation, Kin P. Cheung, National Institute of Standards and Technology
Chapter Article Sponsor: Total Facility Solutions: Download the new issue now!
Total Facility Solutions delivers process-critical infrastructure for semiconductor, life science, photovoltaic, and mission-critical manufacturing and clean room installations. Our turnkey facilities-contracting solutions feature high-purity piping, electrical services, clean utilities, as well as process equipment and gas, chemical and ultra-pure water systems installations, among others. We provide total facility solutions that deliver maximum value and quality to our customers.
Total Facility Solutions Business Development, Total Facility Solutions
Factory Integration: Download the new issue now!
Factory Integration (FI) is one of the key sections of the International Technology Roadmap for Semiconductor (ITRS) that strives to integrate all the factory components in order to efficiently produce the required products in the right volumes on schedule while meeting cost targets. To keep up with the Moore’s Law, it is paramount to sustain the decades-long trend of 30 percent per year reduction in cost per function, which requires capturing all possible factory cost reduction opportunities.
Richard Öchsner, Fraunhofer Institute for Integrated Systems and Device Technology (IISB)
Front End of Line
Introduction: Download the new issue now!
2011 was another year of excitement with relevant progress in new memories, III-V integration, FinFET moving in production, FDSOI showing great performance and additional functionalities like multiple Vt and dynamic Vt control.
Yannick Le Tiec, CEA-Leti
Chapter Article Sponsor: Nikon: Download the new issue now!
Nikon Corporation has been one of the world’s leading optical companies for more than 90 years. Nikon developed the world’s first production-worthy step-and-repeat photolithography tool in 1980. Since then, over half of all integrated circuits printed have been manufactured on Nikon steppers and scanners.
Nikon Corporation
Lithography: Download the new issue now!
Extending optical lithography as we know it beyond 2011 has become increasingly difficult. Single-optical exposure has reached its limit at the 40 nm half-pitch (hp). Thirty-two nm hp Flash devices are being manufactured today using 193 nm double patterning (DP) as a way of extending the half-pitch while keeping the numerical aperture (NA) and wavelength constant. This approach will be pushed harder as DRAM and MPU drive down to the 32 nm hp and Flash starts to test the limits at the 22 nm hp in 2013. It is at this point that non-optical lithography must be introduced into manufacturing to ensure a smooth transition beyond 22 nm. Extreme ultraviolet lithography (EUVL) has been gaining significant momentum with several manufacturers taking delivery of pilot line tools. Some have even announced plans to purchase production tools that will be delivered as early as 2012. If EUVL should not be ready on time, the industry will likely extend DP to multiple patterning (MP). Other non-optical lithography may also be used in a complementary fashion for small-volume applications and/or prototyping.
David Chan, SEMATECH
Chapter Article Sponsor: Hitachi: Download the new issue now!
Hitachi High Technologies America (HTA) supplies state-of-the-art dry plasma etch systems to world-leading SC and HDD manufacturers.
Hitachi High Technologies America, Inc.
Front End Processes: Download the new issue now!
The Front End Processes (FEP) Roadmap focuses on future process requirements and potential solutions related to scaling MOSFETs, DRAM storage capacitors and non-volatile RAM (Flash, phase-change and ferro-electric). The FEP Roadmap encompasses the materials, electrical and physical specifications, tools, as well as the unit and integrated processes starting with the silicon wafer substrate and extending through the contact silicidation processes and the deposition of strain layers.
Joel Barnett, Tokyo Electron America, Raj Jammy, SEMATECH, Mike Walden, SUMCO, Chris Hobbs, SEMATECH
Back End of Line
Introduction: Download the new issue now!
The ITRS Interconnect Group recognizes that copper and low-k dielectric will remain in use over the approaching 15-year horizon. However, scaling of RC due to Cu/low-k has been minimal due to the complexity of integrating ULK materials and the increasing resistivity of shrinking Cu lines.
Sitaram Arkalgud, SEMATECH
Interconnect: Download the new issue now!
The Interconnect Chapter of the ITRS addresses the wiring system that distributes clock and other signals to the various functional blocks of a CMOS integrated circuit, along with providing necessary power and ground connections. The process scope begins at the contact level with the pre-metal dielectric and continues up to the wire bond pads, describing deposition, etch and planarization steps, along with any necessary etches, strips and cleans. A section on reliability and performance includes specifications for electromigration and calculations of delay. The fundamental development requirement for interconnect is to meet the high-bandwidth low-power signaling needs without introducing performance bottlenecks as scaling continues. Although the Interconnect TWG continues to forecast the use of copper as the primary conductor in a dual-damascene architecture through the end of the 15-year forecast horizon, much of the current research and development focuses on new challenges and trends associated with 3D integration, new materials, processes and emerging technology. The 2011 ITRS Chapter contains significant new content on the search for Cu replacements and the need to consider interconnect requirements for the inevitable replacement for the FET switch. Included are more radical options beyond even carbon nanotubes, such as molecular interconnects quantum waves and spin coupling. However, these are all in their nascent phase of development. In any case, the overall goal for interconnects remains: propagating terabits/second at femtojoules/bit.
Paul Zimmerman, Intel Corporation
Metrology, Inspection & Failure Analysis
Introduction: Download the new issue now!
Process control and yield management are critical functions of semiconductor manufacturing that continue to rely on metrology, inspection and failure analysis. Shrinking device dimensions and the introduction of new materials and device structures continue to bring new challenges to overcome.
David Seiler, NIST
Chapter Article Sponsor: Qcept Technologies: Download the new issue now!
Qcept Technologies is the pioneer in non-visual defect (NVD) inspection for the semiconductor industry. Our ChemetriQ® technology is designed to tackle one of the most difficult challenges facing leading-edge as well as mainstream semiconductor device manufacturers—fast detection of yield-critical NVDs.
Qcept Technologies
Yield Enhancement: Download the new issue now!
Yield enhancement is the key to competitive semiconductor manufacturing. In the semiconductor industry, the wafer sort yield is given by the portion of integrated circuits produced within the specifications. Yield Enhancement (YE) for manufacturing of integrated devices addresses the improvement from research and development yield to mature yield in high-volume production. The YE Chapter displays the current and future requirements for high-yielding manufacturing of DRAM, MPU and Flash. Furthermore, it identifies showstoppers for manufacturing and discusses potential solutions.
Lother Pfitzner, Fraunhofer Institute for Integrated Systems and Device Technology (IISB), Andreas Nutsch, Fraunhofer Institute for Integrated Systems and Device Technology (IISB)
Metrology: Download the new issue now!
The continued interest in metrology was evident during 2011. Technical challenges were again accelerated as 3D device structures such as the FinFET and TSVs went from the research stage to manufacturing. The interest was also evident as the Metrology TWG increased participation and replaced key representatives. As with previous years, the Metrology Roadmap is a collaborative effort between the Metrology TWG and the other TWGs. Process requirements are drawn from Emerging Research Materials, Emerging Research Devices, Lithography, FEP, Interconnect, Process Integration, Devices and Structures, and Assembly and Packaging. As a cross-cutting TWG, Metrology also relies on the information from Modeling and Simulation, Yield Enhancement, and Factory Integration.
Alain C. Diebold, CNSE
Assembly, Test & Packaging Technologies
Introduction: Download the new issue now!
This edition of Future Fab presents two articles that discuss the International Technology Roadmap Semiconductors (ITRS) 2011 publication and outline the related packaging and testing sections.
Steve Greathouse, Plexus Corporation
Chapter Article Sponsor: Advantest: Download the new issue now!
Based in Tokyo with subsidiaries around the globe, Advantest Corporation (NYSE: ATE, TSE: 6857) is the world’s foremost manufacturer of automatic test equipment (ATE) for the semiconductor industry, and a leading manufacturer of measuring instruments used in the design, production and maintenance of electronic systems including fiber optic and wireless communications equipment and digital consumer products.
Advantest America Inc.
Test & Test Equipment: Download the new issue now!
Users expect their electronic devices to function properly from the moment the power is turned on until the power is turned off. This expectation is repeated each time the user chooses to use the device. The life of that expectation can be thought of as “forever,” where “forever” is defined as the time when the user moves on to something new and stops using the current device. To have high confidence a device will operate flawlessly as designed, end products must undergo a thorough test that may occur at some point or multiple points in the manufacturing process. To provide the perfect end-user experience, the device also should regularly undergo a background confidence test to notify the user of any potential issue rather than just catastrophically failing.
Roger Barth, Micron, Dave Armstrong, Advantest America Inc.
Assembly & Packaging: Download the new issue now!
The consumer market and consumer-driven electronic devices such as smartphones and tablets have given rise to a multitude of new package architectures to meet the market demands. At the same time, the rise of cloud computing gives impetus to packaging architectures for high-performance network systems and servers to support the double-digit growth of the services from cloud computing.
W.R. Bottoms, Third Millennium Test Solutions, Inc., William T. Chen, ASE (U.S.) Inc.
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