In this issue:
Future Visions & Current Concerns
 Introduction Download the new issue now!
What has been true for the evolution of the animal kingdom has never been truer for the evolution of the nanoelectronics kingdom as well. As scaling of devices has been enabled by the development of new materials and fabrication techniques, increased cost-effectiveness of semiconductor manufacturing has been realized in part by the increase of wafer size.
Alain Kaloyeros, College of Nanoscale Science and Engineering, University at Albany
Chapter Article Sponsor Download the new issue now!
Hitachi High Technologies America (HTA) designs state-of-the-art dry plasma etch tools for world-leading semiconductor and hard disk drive (HDD) manufacturers. Hitachi’s renowned etch technology, paired with unmatched service and support, provides customers with etch solutions to meet their stringent development and production requirements. HTA delivers performance.
Hitachi High Technologies America, Inc.
450 mm Era: A New Opportunity for the Semiconductor Industry Download the new issue now!
The Global 450 Consortium (G450C), announced by New York Governor Andrew M. Cuomo in September 2011 and headquartered at the SUNY College of Nanoscale Science and Engineering (CNSE) in Albany, is leading the industry transition from the 300 mm wafer to 450 mm wafer production. This first-of-its-kind collaboration includes five leading international IC manufacturing companies partnering with CNSE to create the next generation of computer chip technology.
John Lin, G450C, Paul Farrar, G450C
Thought Leadership Profile Download the new issue now!
A truly injury-free workplace is attainable only through a comprehensive shift in corporate culture, having everyone—from part-time contractors to the highest levels of management—all taking responsibility for the end goal: the removal of risk.
Total Facility Solutions Business Development, Total Facility Solutions
Industry Alignment on Cost and Time Savings in the 450 mm Transition Download the new issue now!
The virtues of collaboration in the extraordinarily complex and capital-intensive business of microelectronic technology development have been long recognized and are only becoming more important as transition to manufacturing on 450 mm wafers accelerates.
Commercial wafer fabs are dependent on intricate synchronization and interoperability of hardware, software and other technology that is provided from numerous companies around the world. Both chipmakers and their suppliers benefit from coordinated planning activity. Consequently, the industry has developed many ways to achieve alignment and efficiency, including roadmaps, consortia-facilitated activity and standards development, to name just a few.
Jonathan Davis, SEMI, Frank Robertson, G450C, Allen Ware, M+W Group
Thought Leadership Profile Download the new issue now!
As the process of research and investigation gets into full swing, the enormity of the scale of a 450 mm fab is beginning to come into focus, and with it interesting juxtapositions in relation to the 300 mm transfer back in the early 2000s.
M+W Group Business Development, M+W Group
How to Survive the Scaling and 450 mm Transition Challenge Download the new issue now!
For the past five years, mobile communication and mobile computing have been the main drivers for the IC industry and for the need to scale down transistors. This trend will continue. High-value connectivity will be in the background of everyday lives, connecting people to people and people to their environments. More new opportunities are on the horizon. Chips will be integrated to enable new diagnostic devices for improved, faster and point-of-care diagnostics. These tremendous opportunities to develop a personal health management system, together with the ever-continuing demand for increased connectivity, will drive the IC industry in the coming years.
Luc Van den hove, imec
New Technologies & Device Structures
Introduction Download the new issue now!
The two papers in this section talk about widely differing applications: flexible displays and 10-axis M&NEMS sensors. The common ground, though, is that both are based on new technologies that have been refined and optimized in R&D labs for a long time, and that are now transferred for actual fabrication.
Lode Lauwers, imec
The Robust Plastic Future Is Available Today Download the new issue now!
Recent progress in the development of plastic electronics means that qualified components are now becoming commercially available. Flexible plastic displays in particular are enabling the redesign of many current devices, as well as the development of a whole range of new applications across a broad range of markets and in areas where it might least be expected.
Mike Banach, Plastic Logic Ltd
M&NEMS: A Technological Platform for 10-Axis Sensor Download the new issue now!
MEMS technology has enabled millimeter-scale sensors requiring milliwatt-level power, resulting in the widespread proliferation of sensors in practically all sectors, including industry, consumer, medical, automotive and more. Further reductions in size (and therefore cost) of these MEMS sensors is likely to result in lower performance because simple physics shows that reducing various device parameters (e.g. mass and capacitance) will decrease signal-to-noise ratio (SNR). To overcome the limitations of existing MEMS technology, CEA-Leti has developed a new design and detection mode combining micro- and nano-electromechanical systems (M&NEMS) technologies.
P. Robert, CEA-Leti, P. Rey, CEA-Leti, A. Berthelot, CEA-Leti, G. Jourdan, CEA-Leti, Y. Deimerly, CEA-Leti, S. Louwers, Tronics, J. Bon, Tronics, F.X. Boillot, Tronics, Joël Collet, Tronics
Lithography Landscape
Introduction Download the new issue now!
Additional mask data preparation, called mask process correction (MPC), is required prior to mask exposure. But where should the correction be performed in the mask data flow?
Yayi Wei, GLOBALFOUNDRIES
Section Sponsor Download the new issue now!
Nikon Corporation has been one of the world’s leading optical companies for more than 90 years. Nikon developed the world’s first production-worthy step-and-repeat photolithography tool in 1980. Since then, more than half of all ICs printed have been manufactured on Nikon steppers and scanners.
Nikon Corporation
Shifts for EUV Mask Users and Suppliers Download the new issue now!
The introduction of extreme ultraviolet (EUV) lithography will require paradigm shifts in the relationship between mask users and suppliers because of the new e-beam patterning corrections required by the structure of the EUV mask blank. These corrections will require that pattern modifications similar to optical proximity correction (OPC) be applied by the maskmaker, and that new mask specifications be put in place to support them.
Keith Standiford, GLOBALFOUNDRIES
Back End of Line
Introduction Download the new issue now!
The paper in this Back End of Line section addresses one of the most critical challenges our industry has ever faced. This is not an overstatement, but it is only recently that the severity of this challenge has been fully recognized.
Jon Candelaria, SRC
Interconnect History and Future Prospects: Part 1 Download the new issue now!
In this article, the background and current situation of the interconnect problem are explained. Limits imposed by interconnects on IC performance are described in various perspectives, including power dissipation, resistance-capacitance product and reliability. Potential material-based solutions to mitigate the interconnect problem are underlined. The intrinsic delay and energy-per-bit associated with carbon-based interconnect technologies are compared against Cu/low-k. Various carbon-based interconnect designs are shown to hold promise as nanoscale interconnects.
Ahmet Ceyhan, Georgia Institute of Technology, Azad Naeemi, Georgia Institute of Technology
Metrology, Inspection & Failure Analysis
Introduction Download the new issue now!
This issue’s MIFA section deals with two main topics: A general overview of technical requirements for a future viable metrology (either for 450 mm or to cope with challenges imposed by a 1X nm technology node) is paired with a specific case study of a typical, day-to-day defectivity problem.
Davide Lodi, Micron Semiconductors
The Enabling Role of Metrology in the 450 mm Transition Download the new issue now!
Development of next-generation IC wafer metrology must simultaneously address two major challenges. The first—independent of wafer size and dictated by Moore’s Law—is providing measurement and detection capabilities for continuously decreasing critical dimensions. Detection and measurement of smaller dimensions on increasing topographical complexity drives the need for higher resolution and lower signal-to-noise (S/N) ratio. The second major challenge is dictated by the economics of larger wafer size.
Rand Cottle, G450C, David Nessim, Intel Corporation, Frank Robertson, G450C, Menachem Shoval, Metro450
Addressing Nanodefectivity Challenges Download the new issue now!
As the environment in the semiconductor industry scales to nodes below 20 nm, strict requirements are being put on equipment and material suppliers to address defectivity challenges. Next-generation lithography techniques, new materials and processes for sub-20 nm node manufacturing, and the progression toward 450 mm wafer integration are among the candidates that are affected by these requirements.
Jenah Harris-Jones, SEMATECH
Quantifying Focus Spot-Related Yield Loss Download the new issue now!
Pressure to maximize yield has increased attention on backside wafer cleanliness. To perform adequate cost-benefit analysis for potential backside cleaning methods, the cost in terms of yield must be quantified. A method for quantifying the yield impact of focus spots is presented. Attempts to predict die loss from the measured height of focus spots proved to be of limited value.
Garry Tuohy, GLOBALFOUNDRIES, Inc.
Wafer Fab & Packaging Integration
Introduction Download the new issue now!
First of all, I must admit that I don´t like the naming “2.5D” for interposer technology; for a physicist, 2.5D is an outrageous term. On the other hand, as a technologist, I surely see advantages of interposers against “real” 3D integration: less complex design flow and testing, better thermal management—and potentially lower cost.
Peter Ramm, Fraunhofer EMFT Munich
Section Sponsor Download the new issue now!
Invent. Innovate. Implement. These words summarize EV Group’s mission—to be the first to explore new micro- and nano-fabrication technologies that enable our customers to successfully commercialize new product ideas.
EV Group Business Development, EV Group
Through-Silicon Interposer Technology for Heterogeneous Integration Download the new issue now!
We demonstrate 2.5D through-silicon interposer (TSI) technology development addressing the challenges in versatile memory and logic system integration. We report the fabrication and characterization results of the first wafer after frontside (FS) M2 and backside (BS) RDL integration employing 12 x 100 µm TSV technology in a 300 mm processing line.
H.Y. Li, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), L. Ding, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), G. Katti, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), J.R. Cubillo, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Surya Bhattacharya, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), G.Q. Lo, Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)
3D Stacking: Act II Download the new issue now!
3D chip stacking promises high performance, low power consumption and a small footprint. The technology has made considerable progress in the past few years, with the appearance of the first interposer in 2011 and the first 3D Hybrid Memory Cube (HMC) prototype in early 2013. Adding momentum is the announcement of a global specification for HMC by the HMC Consortium.
Sitaram Arkalgud, Invensas
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