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Friday, August 29, 2014

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Extending ArF Immersion Through Scanner Performance and Computational Lithography

Contributed by Nikon Precision

IC manufacturing technology continues to advance rapidly to meet next-generation requirements. Although integration of EUV lithography has been further delayed due to complex infrastructure issues, the past year has been marked with tremendous innovations in 193 nm scanner technology. Extension of ArF immersion lithography is imperative for chipmakers to maintain their roadmaps, with enhanced tool performance and flexible computational lithography solutions equally critical in extending 193 nm capabilities.

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July 2013 Issue:

Future Visions & Current Concerns

About every 10 years, the semiconductor industry reinvents itself in order to make progress. In this issue of Future Fab International, you will find two significant examples of this innovation process.

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New Technologies & Device Structures

As Future Fab wraps up a distinguished run of service to the international semiconductor community, I would like to take this opportunity to thank my colleagues for offering concise, timely and relevant technology updates and contributions through this publication. Like the phoenix, I trust that new publication opportunities will arise from these ashes that will be well positioned to catch and ride the next tidal waves of emerging technologies.

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Chip Architecture & Integration

For nearly 50 years, Moore’s Law has reliably predicted the doubling of transistors on an integrated circuit every two years. However, in recent years, whispers that “Moore’s Law is dead” abound, as keeping on the technology treadmill bumps up against the limits of physics, economic viability, and the very nature of the application space for semiconductors in a post-PC world.

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Lithography Landscape

In this edition of Future Fab, Yayi Wei and David Cho of GLOBALFOUNDRIES examine the conundrum facing lithographers seeking patterning solutions for the 10 nm node, as the technical and cost challenges of extending 1.35NA 193 nm immersion patterning become more daunting.

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Metrology, Inspection & Failure Analysis

Amid the continued advances of 3D interconnect technology, related improvements in the associated metrology have become ever-more critical.

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Recently, the EDA industry has been challenged to define DFM. Seemingly, this should be a straightforward task, especially with so many companies now marketing DFM solutions. However, the mixed bag of different problems being addressed by the “DFM” companies seems to justify a definition for DFM as being “anything and everything relating to the design of a chip” to be manufactured. DFM product offerings now include reticle enhancement technology (RET), such as optical proximity correction (OPC) to address limits of lithography as well as products to improve OPC results. There are products to address chemical mechanical planarization (CMP) limits of the fabrication process. DFMaware routers are now emerging that improve manufacturability and yield by considering more of the manufacturing process during their execution. There are products to post-analyze layout and routing for manufacturability. DFM solutions are offered for analysis of random defects in fabrication on yield, and emerging are solutions for analyzing the effects of parasitic variations, resulting from process variations, on yield. With these yield solutions is emerging the development of statistical design and analysis tools pushing the DFM scope into other classical EDA areas such as (statistical) timing analysis.
Future Fab Intl.Volume 21, 7/1/2006


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