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July Edition - AVAILABLE NOW! |
"Several studies show that with scaling of technology, the reduced form factor and low power consumption benefits of 3D integrated technology outweigh such challenges as high thermal stress and reliability issues. Here we further investigate performance benefits of 3D in terms of latency and throughput for applications such as many-core architecture."
Awet Yemane Weldezion
KTH Royal Institute of Technology
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In this issue:
Future Visions & Current Concerns
An article describing why standards are needed in the 3D interconnect circuit arena.
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New Technologies & Device Structures
The emerging 3D IC technology using TSVs seems especially suited to implement many-core ICs. But an important challenge will be the physical and logical implementation of power-efficient core-to-core communication that satisfies the very high bandwidth requirements for such future systems.
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Chip Architecture & Integration
Today the semiconductor industry’s biggest challenge threatening progress is the rapidly increasing power dissipation of ICs and systems. As a result, semiconductor companies are increasingly reviewing “2D SoC” roadmaps and contemplating how and when they must transition to a new paradigm to continue meeting customer demands for smarter, faster, lower-power and lower-cost ICs and systems.
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Design Implementation & Process Integration
The promise of 3D chip stacking is indeed huge, revolutionizing the ability to optimize technology choices to meet optimum performance, power and cost. However, chip stacking stresses multiple levels of the existing supply chain, potentially requiring multiple foundries to supply silicon to an OSAT in order to create a finished stacked product. This significantly complicates the existing issues.
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Manufacturing, Systems & Software
In this issue, we further explore the discussion from the last issue that introduced Enhanced Equipment Quality Management (EEQM) and its role in unifying efforts to drive systematic characterization and improvement of equipment quality and performance issues among all the requisite players.
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Front End of Line
Scaling pushes lithography to be able to print smaller and smaller patterns. Cleverness and deep understanding of the optics laws helped to achieve unthinkable results like printing features whose size is below the exposure wavelength.
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Back End of Line
In continuing Future Fab International articles on 3-dimensional integration (3Di), the following two articles mark recent progress on critical 3Di concepts and elements at CEA-Leti and SEMATECH.
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Metrology, Inspection & Failure Analysis
In my professional life, I have read many technology papers that start with the words "The continuous shrinking of chip dimensions…" (drat! I myself wrote some of them!). What may have appeared a rhetorical expedient to start an article, in recent years has become the curse of the technology improvement.
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Wafer Fab & Packaging Integration
Recent advancements in the packaging technology, namely in 3D chip stacking, have stimulated a tremendous growth toward the use of wafer-level processes for packaging integration. As a result, the traditional front-end and back-end segments of the IC industry have practically merged now (as far as process and equipment complexity goes) in the 3D-TSV area, and are ironically called by some of my colleagues at recent wafer-level packaging conferences "middle-end."
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Assembly Test & Packaging Technologies
The following paper by Lee Smith of Amkor gives some of the background and history behind the different types of stacked die and packages that have been utilized by the different designers to allow the overall size reduction and to increase performance of a product.
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Comparison of Final Test Handling Strategies for Massively Parallel Test of Logic Devices
The typical logic IC is tested multiple times in the manufacturing process to screen out and eliminate defects. The first test is at wafer probe to screen out wafer process defects. Once the device is assembled, it is functionally tested to sort out any remaining defects and ensure that published specifications are met. This last or final test can require multiple insertions at different temperature extremes. Additionally, depending on the end user, the IC may be subjected to burn-in at elevated temperatures for lengthy periods of time, then tested again. As one can see, the test process can be very complex and can add significant cost due to cycle time, inventory, and capital equipment requirements.
Future Fab Intl.Volume 12, 2/2/2002
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