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In this issue we are pleased to welcome and to introduce you to the following new members to our already esteemed editorial board: Stephen Buffat - Nantero - Manager, Jordan Valley Innovation Center; Janice Golda - Intel Corp - Director, Lithography Capital Equipment Development; Lode Lauwers - IMEC - Director, Strategic Program Partnerships; Davide Lodi - Numonyx - Manager, Wet Processes & Metrology Engineering ; Kazu Yamada - NEC Electronics America -VP & General Manager, Custom SoC Solutions Strategic Business Unit. Their guidance & wisdom is of course invaluable.
Take a look below to see what you will find in this issue. If you are interested in the content of any of our past issues simply log in and use the left-hand nav buttons to view – it’s easy and it’s FREE.
We hope you enjoy this issue.
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In this issue:
Future Visions & Current Concerns
A look at new opportunities that are emerging to harness chip-based technology for biochemistry and medicine and other applications with dramatically increasing levels of integration. Some challenges that 300 mm manufacturing overcame and some of the anticipated challenges that 450 mm manufacturing must address.
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New Technologies & Device Structures
Silicon photonics builds on the momentum of silicon electronics to deliver to photonic integration what was lacking: a generic integration platform. Will this drive the adoption of photonic integration by a wide range of volume applications with increasing requirements in size, weight and power consumption?
A review of recent results obtained at the University of Texas at Dallas on organic semiconductor-based devices and circuits.
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Design Implementation & Process Integration
Three very different companies from the design, photo-mask and equipment spaces are applying the proverb “it takes a village to raise a child” to create a virtual village to tackle costs. A look and introduction to eDFM and how it will go further to predict and optimize the effects on power performance of chip designs.
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Manufacturing, Systems & Software
A look at ISMI’s Small Carrier Capacity Task Force analysis that quantifies the potential cycle-time benefits to be achieved by implementing equipment improvements, replacing batch equipment with single-wafer processing tools, and adjusting lot cascade lengths. A summary of the obstacles faced by 450 mm wafers and a look at two proposed alternatives.
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Front End of Line
A follow-on from a previously presented overview of the changing nature of reticle electrostatic damage, and the consequences for semiconductor fabs. New data is presented from an experiment that was designed to quantify the damage effects under closely controlled conditions.
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Back End of Line
A look at the scaling trends and subsequent process technology advances in ultrathin barrier/seed layers for Cu interconnect.
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Metrology, Inspection & Failure Analysis
The benefits of using integrated metrology (IM) in terms of improved fab yield, improved process control, automated material handling system (AHMS) and metrology cost reduction, and fab cycle-time improvement. The first of a two-part series that describes the use of a new photo-reflectance technique for the in-line characterization of strain in USJ dopant activation in advanced FEO.L processing
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Wafer Fab & Packaging Integration
A description of a modular approach covering detailed analysis with PDE solvers and more abstract behavioral modeling for support for modeling and simulation for 3D design. Methods and results of a new chip-side-healing technology to boost stability of ultrathin die assembled advanced 3D packages.
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Assembly, Test & Packaging Technologies
The Occam Process: Solderless Assembly and Interconnection of Electronic Packages: details of the Occam process.
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Comparison of Final Test Handling Strategies for Massively Parallel Test of Logic Devices
The typical logic IC is tested multiple times in the manufacturing process to screen out and eliminate defects. The first test is at wafer probe to screen out wafer process defects. Once the device is assembled, it is functionally tested to sort out any remaining defects and ensure that published specifications are met. This last or final test can require multiple insertions at different temperature extremes. Additionally, depending on the end user, the IC may be subjected to burn-in at elevated temperatures for lengthy periods of time, then tested again. As one can see, the test process can be very complex and can add significant cost due to cycle time, inventory, and capital equipment requirements.
Future Fab Intl.Volume 12, 2/2/2002
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